gem5 - gem5

Age	Commit message (Expand)	Author
2018-07-28	arch-riscv: Add xret instructions	Alec Roelke
2018-07-28	arch-riscv: Add support for trap value register	Alec Roelke
2018-07-09	arch-riscv: Fix the srlw and srliw instructions.	Austin Harris
2018-05-12	arch-riscv: Update CSR implementations	Alec Roelke
2018-03-20	riscv: throw IllegalInstFault when decoding invalid instructions	Tuan Ta
2018-02-19	arch-riscv: Fix compressed branch op offset	Alec Roelke
2018-01-16	arch-riscv: Fix floating-poing op classes	Alec Roelke
2018-01-16	arch-riscv: Fix floating-point conversion bugs	Alec Roelke
2018-01-10	arch-riscv: Make use of ImmOp's polymorphism	Alec Roelke
2017-11-29	arch-riscv: Move parts of mem insts out of ISA	Alec Roelke
2017-07-14	riscv: Disambiguate between the C and C++ versions of isnan and isinf.	Gabe Black
2017-07-14	riscv: Fix bugs with RISC-V decoder and detailed CPUs	Alec Roelke
2017-07-11	arch-riscv: Add support for compressed extension RV64C	Alec Roelke
2017-07-11	arch-riscv: Restructure ISA description	Alec Roelke
2017-04-05	riscv: fix Linux problems with LR and SC ops	Alec Roelke
2016-11-30	riscv: [Patch 7/5] Corrected LRSC semantics	Alec Roelke
2016-11-30	riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A	Alec Roelke
2016-11-30	riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD	Alec Roelke
2016-11-30	riscv: [Patch 2/5] Added RISC-V multiply extension RV64M	Alec Roelke
2016-11-30	arch: [Patch 1/5] Added RISC-V base instruction set RV64I	Alec Roelke