| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-07-14 | riscv: Fix bugs with RISC-V decoder and detailed CPUs | Alec Roelke |
| 2017-07-11 | arch-riscv: Add support for compressed extension RV64C | Alec Roelke |
| 2017-07-11 | arch-riscv: Restructure ISA description | Alec Roelke |
| 2017-07-05 | cpu: Simplify the rename interface and use RegId | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | arch, cpu: Architectural Register structural indexing | Nathanael Premillieu |
| 2017-04-05 | riscv: fix Linux problems with LR and SC ops | Alec Roelke |
| 2016-11-30 | riscv: [Patch 7/5] Corrected LRSC semantics | Alec Roelke |
| 2016-11-30 | riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A | Alec Roelke |
| 2016-11-30 | riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD | Alec Roelke |
| 2016-11-30 | arch: [Patch 1/5] Added RISC-V base instruction set RV64I | Alec Roelke |
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index : gem5 | |
| gem5 |
| summaryrefslogtreecommitdiff |