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path: root/src/arch/riscv/isa
AgeCommit message (Expand)Author
2017-12-13cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.Gabe Black
2017-12-07arch-riscv: Move compressed ops out of ISAAlec Roelke
2017-11-30arch-riscv: use sext rather than manual masksAlec Roelke
2017-11-30arch-riscv: Remove spaces around ea_codeAlec Roelke
2017-11-29arch-riscv: Remove static parts of AMOs out of ISAAlec Roelke
2017-11-29arch-riscv: Move parts of mem insts out of ISAAlec Roelke
2017-11-29arch-riscv: Move unknown out of ISA descriptionAlec Roelke
2017-11-29arch-riscv: Move standard ops out of ISAAlec Roelke
2017-11-28arch-riscv: Move static_inst into a directoryAlec Roelke
2017-11-07alpha,arm,mips,power,riscv,sparc,x86: Merge exec decl templates.Gabe Black
2017-11-02alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts.Gabe Black
2017-07-14riscv: Disambiguate between the C and C++ versions of isnan and isinf.Gabe Black
2017-07-14riscv: Fix bugs with RISC-V decoder and detailed CPUsAlec Roelke
2017-07-11arch-riscv: Add support for compressed extension RV64CAlec Roelke
2017-07-11arch-riscv: Restructure ISA descriptionAlec Roelke
2017-07-05cpu: Simplify the rename interface and use RegIdRekai Gonzalez-Alberquilla
2017-07-05arch, cpu: Architectural Register structural indexingNathanael Premillieu
2017-04-05riscv: fix Linux problems with LR and SC opsAlec Roelke
2016-11-30riscv: [Patch 7/5] Corrected LRSC semanticsAlec Roelke
2016-11-30riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64AAlec Roelke
2016-11-30riscv: [Patch 3/5] Added RISCV floating point extensions RV64FDAlec Roelke
2016-11-30riscv: [Patch 2/5] Added RISC-V multiply extension RV64MAlec Roelke
2016-11-30arch: [Patch 1/5] Added RISC-V base instruction set RV64IAlec Roelke