gem5 - gem5

Age	Commit message (Collapse)	Author
2019-05-20	riscv: Add an object file loader for linux.	Gabe Black
	Change-Id: I3accca91cc4e02fa8e3a1169590cbe6696cf05e2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18628 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com>
2019-02-08	riscv: ignore nanosleep syscall	Tuan Ta
	Change-Id: I564a09564da668a5db3e75f15b33efaca363d71a Reviewed-on: https://gem5-review.googlesource.com/c/9624 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-07	arch-riscv: Enable support for riscv 32-bit in SE mode.	Austin Harris
	This patch splits up the riscv SE mode support for 32 and 64-bit. A future patch will add support for decoding rv32 instructions. Change-Id: Ia79ae19f753caf94dc7e5830a6630efb94b419d7 Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/c/15355 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com>
2019-01-22	sim-se: add syscalls related to polling	Brandon Potter
	Fix poll so that it will use the syscall retry capability instead of causing a blocking call. Add the accept and wait4 system calls. Add polling to read to remove deadlocks that occur in the event queue that are caused by blocking system calls. Modify the write system call to return an error number in case of error. Change-Id: I0b4091a2e41e4187ebf69d63e0088f988f37d5da Reviewed-on: https://gem5-review.googlesource.com/c/12115 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-01-05	arch-riscv: Ignore sched_yield syscall in SE mode	Tuan Ta
	Change-Id: I14f22c06eb8fdbe063980b4cd0a49387b9113a97 Reviewed-on: https://gem5-review.googlesource.com/6961 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
2018-01-05	arch-riscv: Ignore set_robust_list and get_robust_list syscalls	Tuan Ta
	Change-Id: I5a4744e5aed07337144af9f07978b83405b6695b Reviewed-on: https://gem5-review.googlesource.com/6902 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2018-01-05	arch-riscv: Add an implementation of set_tid_address syscall in RISCV	Tuan Ta
	Change-Id: Ida29ea6f6a9c3efe00aaebbfcb6b537fc62f6d06 Reviewed-on: https://gem5-review.googlesource.com/6901 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-22	arch-riscv: Add missing system calls	Alec Roelke
	This patch adds all system calls present in riscv-gnu-toolchain at commit hash 65cb174. Many of them do not have implementations in gem5, so they are just placeholders. [Remove the variadic macro and replace it with a function that has default arguments because variadic macros may not be portable across compilers] [Remove spaces around default arguments of createSyscall for better style] [Switch from using a loose function to using SyscallDesc's new constructor] Change-Id: Iff97c689109121b39df423c72d0e79c6366e31b9 Reviewed-on: https://gem5-review.googlesource.com/5322 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2016-11-09	syscall_emul: [patch 5/22] remove LiveProcess class and use Process instead	Brandon Potter
	The EIOProcess class was removed recently and it was the only other class which derived from Process. Since every Process invocation is also a LiveProcess invocation, it makes sense to simplify the organization by combining the fields from LiveProcess into Process.
2016-11-09	syscall_emul: [patch 2/22] move SyscallDesc into its own .hh and .cc	Brandon Potter
	The class was crammed into syscall_emul.hh which has tons of forward declarations and template definitions. To clean it up a bit, moved the class into separate files and commented the class with doxygen style comments. Also, provided some encapsulation by adding some accessors and a mutator. The syscallreturn.hh file was renamed syscall_return.hh to make it consistent with other similarly named files in the src/sim directory. The DPRINTF_SYSCALL macro was moved into its own header file with the include the Base and Verbose flags as well. --HG-- rename : src/sim/syscallreturn.hh => src/sim/syscall_return.hh
2016-11-30	riscv: [Patch 6/5] Improve Linux emulation for RISC-V	Alec Roelke
	This is an add-on patch for the original series that implemented RISC-V that improves the implementation of Linux emulation for SE mode. Basically it cleans up linux/linux.hh by removing constants that haven't been defined for the RISC-V Linux proxy kernel and rearranging the stat struct so it aligns with RISC-V's implementation of it. It also adds placeholders for system calls that have been given numbers in RISC-V but haven't been given implementations yet. These system calls are as follows: - readlinkat - sigprocmask - ioctl - clock_gettime - getrusage - getrlimit - setrlimit The first five patches implemented RISC-V with the base ISA and multiply, floating point, and atomic extensions and added support for detailed CPU models with memory timing. [Fixed incompatibility with changes made from patch 1.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com>
2016-11-30	arch: [Patch 1/5] Added RISC-V base instruction set RV64I	Alec Roelke
	First of five patches adding RISC-V to GEM5. This patch introduces the base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation. The multiply, floating point, and atomic memory instructions will be added in additional patches, as well as support for more detailed CPU models. The loader is also modified to be able to parse RISC-V ELF files, and a "Hello world\!" example for RISC-V is added to test-progs. Patch 2 will implement the multiply extension, RV64M; patch 3 will implement the floating point (single- and double-precision) extensions, RV64FD; patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches (such as handling locked memory). [Removed several unused parameters and imports from RiscvInterrupts.py, RiscvISA.py, and RiscvSystem.py.] [Fixed copyright information in RISC-V files copied from elsewhere that had ARM licenses attached.] [Reorganized instruction definitions in decoder.isa so that they are sorted by opcode in preparation for the addition of ISA extensions M, A, F, D.] [Fixed formatting of several files, removed some variables and instructions that were missed when moving them to other patches, fixed RISC-V Foundation copyright attribution, and fixed history of files copied from other architectures using hg copy.] [Fixed indentation of switch cases in isa.cc.] [Reorganized syscall descriptions in linux/process.cc to remove large number of repeated unimplemented system calls and added implmementations to functions that have received them since it process.cc was first created.] [Fixed spacing for some copyright attributions.] [Replaced the rest of the file copies using hg copy.] [Fixed style check errors and corrected unaligned memory accesses.] [Fix some minor formatting mistakes.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com>