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path: root/src/arch/riscv/process.cc
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2017-05-23arch-riscv: Fix bad stack initializationAlec Roelke
This patch fixes a problem with RISC-V initial stack setup in SE mode where the AT_RANDOM aux vector value contains an address that is too close to the top of the stack and doesn't fit the required 16 bytes. To fix this, the program header table was added to the top of the stack just like the RISC-V proxy kernel does. Change-Id: I814562e060ff041cd0d7a7c54c3685645bd325a3 Reviewed-on: https://gem5-review.googlesource.com/3401 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-04-11riscv: Fix crashes with large or frequent mmapsAlec Roelke
This patch fixes a bug where increasing the mmap region too much causes it to run into already-allocated memory, which causes gem5 to fail an assertion. Previously, the stack was incorrectly set up such that the end of the mmap region and the top of the stack were the same address and both would grow downward. With this patch, the top of the stack has been separated from the end of mmap and moved up, and the mmap region now grows upward instead of downward. [Rebase to master branch and remove dependencies.] Change-Id: I7271ff478fff2994f918bc5003a6139b9ba6a520 Reviewed-on: https://gem5-review.googlesource.com/2680 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05riscv: fix compatibility with Linux toolchainAlec Roelke
Previously, RISC-V in gem5 only supported RISC-V's Newlib toolchain (riscv64-unknown-elf-*) due to incorrect assumptions made in the initial setup of the user stack in SE mode. This patch fixes that by referring to the RISC-V proxy kernel code (https://github.com/riscv/riscv-pk) and setting up the stack according to how it does it. Now binaries compiled using the Linux toolchain (riscv64-unknown-linux-gnu-*) will run as well. [Update for recent changes to MemState to add accessors and mutators to get its members.] Change-Id: I6d2c486df7688efe3df54273e9aa0fd686851285 Reviewed-on: https://gem5-review.googlesource.com/2305 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-03-09syscall-emul: Move memState into its own fileBrandon Potter
The Process class is full of implementation details and structures related to SE Mode. This changeset factors out an internal class from Process and moves it into a separate file. The purpose behind doing this is to clean up the code and make it a bit more modular. Change-Id: Ic6941a1657751e8d51d5b6b1dcc04f1195884280 Reviewed-on: https://gem5-review.googlesource.com/2263 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-02-27syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess ↵Brandon Potter
simulations Modifies the clone system call and adds execve system call. Requires allowing processes to steal thread contexts from other processes in the same system object and the ability to detach pieces of process state (such as MemState) to allow dynamic sharing.
2016-11-09syscall_emul: [patch 8/22] refactor process classBrandon Potter
Moves aux_vector into its own .hh and .cc files just to get it out of the already crowded Process files. Arguably, it could stay there, but it's probably better just to move it and give it files. The changeset looks ugly around the Process header file, but the goal here is to move methods and members around so that they're not defined randomly throughout the entire header file. I expect this is likely one of the reasons why I several unused variables related to this class. So, the methods are declared first followed by members. I've tried to aggregate them together so that similar entries reside near one another. There are other changes coming to this code so this is by no means the final product.
2016-11-09syscall_emul: [patch 5/22] remove LiveProcess class and use Process insteadBrandon Potter
The EIOProcess class was removed recently and it was the only other class which derived from Process. Since every Process invocation is also a LiveProcess invocation, it makes sense to simplify the organization by combining the fields from LiveProcess into Process.
2017-01-27riscv: Fix crash when syscall argument reg index is too highAlec Roelke
By default, doSyscall gets the values of six registers to be used for system call arguments. RISC-V, by convention, only has four. Because RISC-V's implementation of these indices is as arrays of integers rather than as base indices plus offsets, trying to get the fifth argument register's value will cause a crash. This patch fixes that by returning 0 for any index higher than 3. Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2016-11-09style: [patch 3/22] reduce include dependencies in some headersBrandon Potter
Used cppclean to help identify useless includes and removed them. This involved erroneously included headers, but also cases where forward declarations could have been used rather than a full include.
2016-11-30arch: [Patch 1/5] Added RISC-V base instruction set RV64IAlec Roelke
First of five patches adding RISC-V to GEM5. This patch introduces the base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation. The multiply, floating point, and atomic memory instructions will be added in additional patches, as well as support for more detailed CPU models. The loader is also modified to be able to parse RISC-V ELF files, and a "Hello world\!" example for RISC-V is added to test-progs. Patch 2 will implement the multiply extension, RV64M; patch 3 will implement the floating point (single- and double-precision) extensions, RV64FD; patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches (such as handling locked memory). [Removed several unused parameters and imports from RiscvInterrupts.py, RiscvISA.py, and RiscvSystem.py.] [Fixed copyright information in RISC-V files copied from elsewhere that had ARM licenses attached.] [Reorganized instruction definitions in decoder.isa so that they are sorted by opcode in preparation for the addition of ISA extensions M, A, F, D.] [Fixed formatting of several files, removed some variables and instructions that were missed when moving them to other patches, fixed RISC-V Foundation copyright attribution, and fixed history of files copied from other architectures using hg copy.] [Fixed indentation of switch cases in isa.cc.] [Reorganized syscall descriptions in linux/process.cc to remove large number of repeated unimplemented system calls and added implmementations to functions that have received them since it process.cc was first created.] [Fixed spacing for some copyright attributions.] [Replaced the rest of the file copies using hg copy.] [Fixed style check errors and corrected unaligned memory accesses.] [Fix some minor formatting mistakes.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com>