| Age | Commit message (Expand) | Author |
|---|
| 2019-02-08 | riscv: fixed syscall return value | Tuan Ta |
| 2019-02-07 | arch-riscv: Enable support for riscv 32-bit in SE mode. | Austin Harris |
| 2019-01-31 | riscv: Get rid of some ISA specific register types. | Gabe Black |
| 2018-09-19 | syscall_emul: expand AuxVector class | Brandon Potter |
| 2018-05-12 | arch-riscv: Update CSR implementations | Alec Roelke |
| 2018-01-19 | arch, mem, sim: Consolidate and rename the SE mode page table classes. | Gabe Black |
| 2018-01-15 | arch: Fix a fatal_if in most of the arch's process classes. | Gabe Black |
| 2018-01-11 | arch,mem: Remove the default value for page size. | Gabe Black |
| 2018-01-11 | arch,mem: Move page table construction into the arch classes. | Gabe Black |
| 2018-01-04 | arch-riscv: Remove "magic" syscall number constant | Alec Roelke |
| 2017-12-14 | arch-riscv: Define AT_RANDOM properly | Alec Roelke |
| 2017-12-14 | arch-riscv: Increase maximum stack size | Alec Roelke |
| 2017-12-04 | misc: Rename misc.(hh|cc) to logging.(hh|cc) | Gabe Black |
| 2017-05-23 | arch-riscv: Fix bad stack initialization | Alec Roelke |
| 2017-04-11 | riscv: Fix crashes with large or frequent mmaps | Alec Roelke |
| 2017-04-05 | riscv: fix compatibility with Linux toolchain | Alec Roelke |
| 2017-03-09 | syscall-emul: Move memState into its own file | Brandon Potter |
| 2017-02-27 | syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess s... | Brandon Potter |
| 2016-11-09 | syscall_emul: [patch 8/22] refactor process class | Brandon Potter |
| 2016-11-09 | syscall_emul: [patch 5/22] remove LiveProcess class and use Process instead | Brandon Potter |
| 2017-01-27 | riscv: Fix crash when syscall argument reg index is too high | Alec Roelke |
| 2016-11-09 | style: [patch 3/22] reduce include dependencies in some headers | Brandon Potter |
| 2016-11-30 | arch: [Patch 1/5] Added RISC-V base instruction set RV64I | Alec Roelke |
