| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-07-28 | arch-riscv: Add xret instructions | Alec Roelke |
| 2018-05-12 | arch-riscv: Update CSR implementations | Alec Roelke |
| 2018-01-05 | arch-riscv: Correct syscall argument reg count | Alec Roelke |
| 2017-07-17 | riscv: Define register index constants using literals | Alec Roelke |
| 2017-07-14 | riscv: Add unused attribute to some registers.hh constants | Alec Roelke |
| 2017-07-11 | arch-riscv: Restructure ISA description | Alec Roelke |
| 2017-07-05 | cpu: Added interface for vector reg file | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | arch, cpu: Architectural Register structural indexing | Nathanael Premillieu |
| 2017-04-05 | riscv: add remote gdb support | Alec Roelke |
| 2017-03-09 | syscall-emul: Rewrite system call exit code | Brandon Potter |
| 2016-11-30 | riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A | Alec Roelke |
| 2016-11-30 | riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD | Alec Roelke |
| 2016-11-30 | arch: [Patch 1/5] Added RISC-V base instruction set RV64I | Alec Roelke |
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| gem5 |
| summaryrefslogtreecommitdiff |