summaryrefslogtreecommitdiff
path: root/src/arch/riscv/registers.hh
AgeCommit message (Expand)Author
2018-07-28arch-riscv: Add xret instructionsAlec Roelke
2018-05-12arch-riscv: Update CSR implementationsAlec Roelke
2018-01-05arch-riscv: Correct syscall argument reg countAlec Roelke
2017-07-17riscv: Define register index constants using literalsAlec Roelke
2017-07-14riscv: Add unused attribute to some registers.hh constantsAlec Roelke
2017-07-11arch-riscv: Restructure ISA descriptionAlec Roelke
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
2017-07-05arch, cpu: Architectural Register structural indexingNathanael Premillieu
2017-04-05riscv: add remote gdb supportAlec Roelke
2017-03-09syscall-emul: Rewrite system call exit codeBrandon Potter
2016-11-30riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64AAlec Roelke
2016-11-30riscv: [Patch 3/5] Added RISCV floating point extensions RV64FDAlec Roelke
2016-11-30arch: [Patch 1/5] Added RISC-V base instruction set RV64IAlec Roelke