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2018-05-12arch-riscv: Update CSR implementationsAlec Roelke
This patch updates the CSRs to match the RISC-V privileged specification version 1.10. As interrupts, faults, and privilege levels are not yet supported, there are no meaninful side effects that are implemented. Performance counters are also not yet implemented, as they do not have specifications. Currently they act as cycle counters. Note that this implementation trusts software to use the registers properly. Access protection, readability, and writeability of registers based on privilege will come in a future patch. Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a Reviewed-on: https://gem5-review.googlesource.com/7441 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2018-01-20arch, mem: Make the page table lookup function return a pointer.Gabe Black
This avoids having a copy in the lookup function itself, and the declaration of a lot of temporary TLB entry pointers in callers. The gpu TLB seems to have had the most dependence on the original signature of the lookup function, partially because it was relying on a somewhat unsafe copy to a TLB entry using a base class pointer type. Change-Id: I8b1cf494468163deee000002d243541657faf57f Reviewed-on: https://gem5-review.googlesource.com/7343 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-20sim, arch, base: Refactor the base remote GDB class.Gabe Black
Fold the GDBListener class into the main BaseRemoteGDB class, move around a bunch of functions, convert a lot of internal functions to be private, move some functions into the .cc, make some functions non-virtual which didn't really need to be overridden. Change-Id: Id0832b730b0fdfb2eababa5067e72c66de1c147d Reviewed-on: https://gem5-review.googlesource.com/7422 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-05-18base: Refactor the GDB code.Gabe Black
The new version modularizes the implementation of the various commands, gets rid of dynamic allocation of the register cache, fixes some small style problems, and uses exceptions to simplify error handling internal to the GDB stub. Change-Id: Iff3548373ce4adfb99106a810f5713b769df89b2 Reviewed-on: https://gem5-review.googlesource.com/3280 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Boris Shingarov <shingarov@gmail.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-04-05riscv: add remote gdb supportAlec Roelke
This patch adds support for debugging with remote GDB to RISC-V. Using GDB compiled with the RISC-V GNU toolchain, it is possible to pause and continue execution, view debugging information, etc. As with the rest of RISC-V, this does not support full-system mode. Change-Id: I2d3a8be614725e1be4b4c283f9fb678a0a30578d Reviewed-on: https://gem5-review.googlesource.com/2304 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2016-11-30arch: [Patch 1/5] Added RISC-V base instruction set RV64IAlec Roelke
First of five patches adding RISC-V to GEM5. This patch introduces the base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation. The multiply, floating point, and atomic memory instructions will be added in additional patches, as well as support for more detailed CPU models. The loader is also modified to be able to parse RISC-V ELF files, and a "Hello world\!" example for RISC-V is added to test-progs. Patch 2 will implement the multiply extension, RV64M; patch 3 will implement the floating point (single- and double-precision) extensions, RV64FD; patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches (such as handling locked memory). [Removed several unused parameters and imports from RiscvInterrupts.py, RiscvISA.py, and RiscvSystem.py.] [Fixed copyright information in RISC-V files copied from elsewhere that had ARM licenses attached.] [Reorganized instruction definitions in decoder.isa so that they are sorted by opcode in preparation for the addition of ISA extensions M, A, F, D.] [Fixed formatting of several files, removed some variables and instructions that were missed when moving them to other patches, fixed RISC-V Foundation copyright attribution, and fixed history of files copied from other architectures using hg copy.] [Fixed indentation of switch cases in isa.cc.] [Reorganized syscall descriptions in linux/process.cc to remove large number of repeated unimplemented system calls and added implmementations to functions that have received them since it process.cc was first created.] [Fixed spacing for some copyright attributions.] [Replaced the rest of the file copies using hg copy.] [Fixed style check errors and corrected unaligned memory accesses.] [Fix some minor formatting mistakes.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com>