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2020-02-01arch,sim: Merge initCPU into the ISA System classes.Gabe Black
Those classes are already ISA specific, so we can just move initCPU's contents there and take it out of utility.hh, utility.cc, and the base System's initState. Change-Id: I28f0d0b50d83efe5116b0b24d20f8182a02823e7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24905 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-02-01arch,sim: Merge initCPU and startupCPU.Gabe Black
These two functions were called in exactly one place one right after the other, and served similar purposes. This change merges them together, and cleans them up slightly. It also removes checks for FullSystem, since those functions are only called in full system to begin with. Change-Id: I214f7d2d3f88960dccb5895c1241f61cd78716a8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24904 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2018-07-09arch-riscv: enable rudimentary fs simulationRobert
These changes enable a simple binary to be simulated in full system mode. Additionally, a new fault was implemented. It is executed once the CPU is initialized. This fault clears all interrupts and sets the pc to a reset vector. Change-Id: I50cfac91a61ba39a6ef3d38caca8794073887c88 Reviewed-on: https://gem5-review.googlesource.com/9061 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>