| Age | Commit message (Expand) | Author |
|---|
| 2017-11-07 | alpha,arm,mips,power,riscv,sparc,x86: Merge exec decl templates. | Gabe Black |
| 2017-11-02 | alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts. | Gabe Black |
| 2017-10-17 | scons: Stop generating inc.d in the isa parser. | Gabe Black |
| 2017-10-13 | mem: Signal the local monitor when clearing the global monitor | Nikos Nikoleris |
| 2017-09-11 | stats: Get rid of some kernel stats related cruft. | Gabe Black |
| 2017-07-17 | riscv: Define register index constants using literals | Alec Roelke |
| 2017-07-14 | riscv: Disambiguate between the C and C++ versions of isnan and isinf. | Gabe Black |
| 2017-07-14 | riscv: Fix bugs with RISC-V decoder and detailed CPUs | Alec Roelke |
| 2017-07-14 | riscv: Add unused attribute to some registers.hh constants | Alec Roelke |
| 2017-07-11 | arch-riscv: Add support for compressed extension RV64C | Alec Roelke |
| 2017-07-11 | arch-riscv: Restructure ISA description | Alec Roelke |
| 2017-07-05 | cpu: Added interface for vector reg file | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | cpu: Simplify the rename interface and use RegId | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | arch, cpu: Architectural Register structural indexing | Nathanael Premillieu |
| 2017-05-23 | arch-riscv: Fix bad stack initialization | Alec Roelke |
| 2017-05-18 | base: Refactor the GDB code. | Gabe Black |
| 2017-05-18 | syscall_emul, riscv: add override keyword to RISCV Process class | Brandon Potter |
| 2017-04-11 | riscv: Fix crashes with large or frequent mmaps | Alec Roelke |
| 2017-04-05 | riscv: fix Linux problems with LR and SC ops | Alec Roelke |
| 2017-04-05 | riscv: fix compatibility with Linux toolchain | Alec Roelke |
| 2017-04-05 | riscv: add remote gdb support | Alec Roelke |
| 2017-04-05 | riscv: fix error on memory op address overflow | Alec Roelke |
| 2017-04-05 | riscv: enable unaligned memory accesses | Alec Roelke |
| 2017-03-09 | syscall-emul: Rewrite system call exit code | Brandon Potter |
| 2017-03-09 | syscall-emul: Move memState into its own file | Brandon Potter |
| 2017-02-27 | syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess s... | Brandon Potter |
| 2015-07-20 | syscall_emul: [patch 13/22] add system call retry capability | Brandon Potter |
| 2016-11-09 | syscall_emul: [patch 8/22] refactor process class | Brandon Potter |
| 2016-11-09 | syscall_emul: [patch 5/22] remove LiveProcess class and use Process instead | Brandon Potter |
| 2017-01-27 | riscv: Fix crash when syscall argument reg index is too high | Alec Roelke |
| 2016-11-09 | style: [patch 3/22] reduce include dependencies in some headers | Brandon Potter |
| 2016-11-09 | syscall_emul: [patch 2/22] move SyscallDesc into its own .hh and .cc | Brandon Potter |
| 2016-11-30 | riscv: [Patch 7/5] Corrected LRSC semantics | Alec Roelke |
| 2016-11-30 | riscv: [Patch 6/5] Improve Linux emulation for RISC-V | Alec Roelke |
| 2016-11-30 | riscv: [Patch 5/5] Added missing support for timing CPU models | Alec Roelke |
| 2016-11-30 | riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A | Alec Roelke |
| 2016-11-30 | riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD | Alec Roelke |
| 2016-11-30 | riscv: [Patch 2/5] Added RISC-V multiply extension RV64M | Alec Roelke |
| 2016-11-30 | arch: [Patch 1/5] Added RISC-V base instruction set RV64I | Alec Roelke |
