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2018-01-10arch-riscv: Make use of ImmOp's polymorphismAlec Roelke
This patch makes use of ImmOp's polymorphism to remove unnecessary casting from the implementations of arithmetic instructions with immediate operands and to remove the CUIOp format by combining it with the CIOp format (compressed arithmetic instructions with immediate operands). Interestingly, RISC-V specifies that instructions with unsigned immediate operands still need to sign-extend the immediates from 12 (or 20) bits to 64 bits, so that is left alone. Change-Id: If20d70c1e90f379b9ed8a4155b2b9222b6defe16 Reviewed-on: https://gem5-review.googlesource.com/6401 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tuan Ta <qtt2@cornell.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2018-01-10alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.Gabe Black
This constant is, first, a #define, and second only used in one place. In that one place, it appears that the code it guards is no longer necessary in general. It was originally written to avoid refetching a block of data that you're still in, even if you've moved slightly farther in it because you're skipping the next instruction due to an annulled branch delay slot. In reality however, in SPARC, the one ISA I'm aware of which has this sort of branching behavior, the PC state object will correctly determine that no branch is happening in these cases. Code lower down in the loop will then recompute where fetching should continue based on the next PC, automatically skipping the annulled branch slot without misinterpretting the gap as a branch. This change therefore also removes this block of code. Change-Id: I820ebc9df10aeb4fcb69c12f6a784e9ec616743c Reviewed-on: https://gem5-review.googlesource.com/6821 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-05arch-riscv: Ignore sched_yield syscall in SE modeTuan Ta
Change-Id: I14f22c06eb8fdbe063980b4cd0a49387b9113a97 Reviewed-on: https://gem5-review.googlesource.com/6961 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
2018-01-05arch-riscv: Ignore set_robust_list and get_robust_list syscallsTuan Ta
Change-Id: I5a4744e5aed07337144af9f07978b83405b6695b Reviewed-on: https://gem5-review.googlesource.com/6902 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2018-01-05arch-riscv: Add an implementation of set_tid_address syscall in RISCVTuan Ta
Change-Id: Ida29ea6f6a9c3efe00aaebbfcb6b537fc62f6d06 Reviewed-on: https://gem5-review.googlesource.com/6901 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2018-01-05arch-riscv: Correct syscall argument reg countAlec Roelke
As per the discussion in patch #6904 and the Linux 4.15 kernel code for RISC-V, RISC-V has 7 system call argument registers, x10 through x16 (a0 through a6), with x17 (a7) being used for the system call number. Change-Id: I0080eca78ffa844b322bb2cff2a51ab2815f3809 Reviewed-on: https://gem5-review.googlesource.com/7081 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tuan Ta <qtt2@cornell.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2018-01-04arch-riscv: Remove "magic" syscall number constantAlec Roelke
getSyscallArg() in RISC-V has an explicit check to make sure that the register index is within the bounds of the system call register indices vector. This patch fixes it so that it uses SyscallArgumentRegs.size() rather than a "magic" constant that has to be updated every time SyscallArgumentRegs is changed. Change-Id: I2935d811177dc8028cb3df64b250ba997bc970d8 Reviewed-on: https://gem5-review.googlesource.com/7061 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-12-23alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst.Gabe Black
It's no longer used. Change-Id: I4a71bcb214f1bb186b92ef50841eca635e6701c5 Reviewed-on: https://gem5-review.googlesource.com/6826 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-23riscv,x86: Stop using the arch Nop machine instruction unnecessarily.Gabe Black
That particular ExtMachInst is a convenient placeholder, but a value of 0 in RISCV or a static uninitialized ExtMachInst (which will therefore be all zeroes) on x86 works just as well, and removes the need for an ISA specific constant. Also, the idea of a universal Nop doesn't always make sense since it could be that what, exactly, doesn't do anything depends on context which would be lost on a constant value of an ExtMachInst. For instance, the value of an ExtMachInst that makes sense might depend on what mode the CPU was in, etc. Change-Id: I1f1a43a5c607a667e11b79bcf6e059e4f7141b3f Reviewed-on: https://gem5-review.googlesource.com/6825 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-22arch,cpu: "virtualize" the TLB interface.Gabe Black
CPUs have historically instantiated the architecture specific version of the TLBs to avoid a virtual function call, making them a little bit more dependent on what the current ISA is. Some simple performance measurement, the x86 twolf regression on the atomic CPU, shows that there isn't actually any performance benefit, and if anything the simulator goes slightly faster (although still within margin of error) when the TLB functions are virtual. This change switches everything outside of the architectures themselves to use the generic BaseTLB type, and then inside the ISA for them to cast that to their architecture specific type to call into architecture specific interfaces. The ARM TLB needed the most adjustment since it was using non-standard translation function signatures. Specifically, they all took an extra "type" parameter which defaulted to normal, and translateTiming returned a Fault. translateTiming actually doesn't need to return a Fault because everywhere that consumed it just stored it into a structure which it then deleted(?), and the fault is stored in the Translation object when the translation is done. A little more work is needed to fully obviate the arch/tlb.hh header, so the TheISA::TLB type is still visible outside of the ISAs. Specifically, the TlbEntry type is used in the generic PageTable which lives in src/mem. Change-Id: I51b68ee74411f9af778317eff222f9349d2ed575 Reviewed-on: https://gem5-review.googlesource.com/6921 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-14arch-riscv: Define AT_RANDOM properlyAlec Roelke
According to the getauxval(3) man page, the AT_RANDOM aux value should be a pointer to 16 random bytes. In the initial implementation of RISC-V, this was based on spike's program stack setup, which copied the program header table there instead. This patch changes the implementation to use the proper 16 random bytes, making it compatible with some RISC-V programs that use custom linker scripts. Change-Id: Idaae7f19bf3ed3fd06d293e5e9c0b6f778270eb2 Reviewed-on: https://gem5-review.googlesource.com/6681 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-12-14arch-riscv: Increase maximum stack sizeAlec Roelke
This patch increases the maximum stack size of RISC-V, which should help to reduce problems with programs that allocate large amounts of data on the stack or do many small allocations. Change-Id: I1d760050229b12f01a4a8f24c047b587299fef6d Reviewed-on: https://gem5-review.googlesource.com/6661 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-12-13cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.Gabe Black
Neither of these were used, particularly memAccInst. Change-Id: I4ac9e44cf624e5de42519d586d7b699f08a2cdfc Reviewed-on: https://gem5-review.googlesource.com/6601 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-07arch-riscv: Move compressed ops out of ISAAlec Roelke
This patch moves static portions of the compressed instruction definitions out of the ISA generated code. Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296 Reviewed-on: https://gem5-review.googlesource.com/6026 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-12-04misc: Rename misc.(hh|cc) to logging.(hh|cc)Gabe Black
These files aren't a collection of miscellaneous stuff, they're the definition of the Logger interface, and a few utility macros for calling into that interface (panic, warn, etc.). Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1 Reviewed-on: https://gem5-review.googlesource.com/6226 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-11-30arch-riscv: use sext rather than manual masksAlec Roelke
Replace manual creation of masks for sign extension of immediates with the sext<N> function. Change-Id: Ief2df91a25500c64f5bcae0dcd437c1e3bb95e6c Reviewed-on: https://gem5-review.googlesource.com/6182 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-30arch-riscv: Remove spaces around ea_codeAlec Roelke
This patch makes mem.isa conform to style guidelines better by removing spaces around the "ea_code" argument default value assignment of the Load format. Change-Id: I1c62b99de3617a3734b128b00fb421773e021317 Reviewed-on: https://gem5-review.googlesource.com/6181 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-29arch-riscv: Add missing license paragraphsAlec Roelke
Some of the files in earlier patches rearranging instruction definitions were missing copyright and license information. This patch adds them. Change-Id: I2ac4910a415de6032fc0b7d4422904c682e0ad87 Reviewed-on: https://gem5-review.googlesource.com/6183 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-11-29arch-riscv: Remove static parts of AMOs out of ISAAlec Roelke
This patch removes the static parts of the RISC-V atomic memory instructions out of the ISA generated code and into arch/riscv/insts. It also makes the LR and SC instructions subclasses of MemInst from arch/riscv/insts/mem.hh. Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51 Reviewed-on: https://gem5-review.googlesource.com/6025 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-29arch-riscv: Move parts of mem insts out of ISAAlec Roelke
This patch moves static portions of the memory instructions out of the ISA generated code and puts them into arch/riscv/insts. It also simplifies the definitions of load and store instructions by giving them a common base class. Change-Id: Ic6930cbfc6bb02e4b3477521e57b093eac0c8803 Reviewed-on: https://gem5-review.googlesource.com/6024 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-29arch-riscv: Move unknown out of ISA descriptionAlec Roelke
This patch removes the Unknown instruction type out of the ISA generated code and puts it into arch/riscv/insts. Since there isn't any dynamic behavior to it, all that's left behind is a template for creating a new Unknown instruction. Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db Reviewed-on: https://gem5-review.googlesource.com/6023 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-29arch-riscv: Move standard ops out of ISAAlec Roelke
This patch removes static portions of the standard instruction types from the generated ISA code and puts them into arch/riscv/insts. Some dynamically-generated content is left behind for each individual instruction's implementation. Also, BranchOp is removed due to its similarity with ImmOp and ImmOp and UImmOp are joined into a single templated class, ImmOp<T>. Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a Reviewed-on: https://gem5-review.googlesource.com/6022 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-28arch-riscv: Move static_inst into a directoryAlec Roelke
This patch creates an "insts" directory in src/arch/riscv to store static portions of instruction definitions that aren't part of the code generated by the ISA description. It serves as a starting point for future patches to simplify the ISA description. Change-Id: I6700522143f6fa6c9b18a30e1fbdc8f80cdc7afa Reviewed-on: https://gem5-review.googlesource.com/6021 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-22arch-riscv: Add missing system callsAlec Roelke
This patch adds all system calls present in riscv-gnu-toolchain at commit hash 65cb174. Many of them do not have implementations in gem5, so they are just placeholders. [Remove the variadic macro and replace it with a function that has default arguments because variadic macros may not be portable across compilers] [Remove spaces around default arguments of createSyscall for better style] [Switch from using a loose function to using SyscallDesc's new constructor] Change-Id: Iff97c689109121b39df423c72d0e79c6366e31b9 Reviewed-on: https://gem5-review.googlesource.com/5322 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-07alpha,arm,mips,power,riscv,sparc,x86: Merge exec decl templates.Gabe Black
In the ISA instruction definitions, some classes were declared with execute, etc., functions outside of the main template because they had CPU specific signatures and would need to be duplicated with each CPU plugged into them. Now that the instructions always just use an ExecContext, there's no reason for those templates to be separate. This change folds those templates together. Change-Id: I13bda247d3d1cc07c0ea06968e48aa5b4aace7fa Reviewed-on: https://gem5-review.googlesource.com/5401 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-02alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts.Gabe Black
The ISA parser used to generate different copies of exec functions for each exec context class a particular CPU wanted to use. That's since been changed so that those functions take a pointer to the base ExecContext, so the code which would generate those extra functions can be removed, and some functions which used to be templated on an ExecContext subclass can be untemplated, or minimally less templated. Now that some functions aren't going to be instantiated multiple times with different signatures, there are also opportunities to collapse templates and make many instruction definitions simpler within the parser. Since those changes will be less mechanical, they're left for later changes and will probably be done in smaller increments. Change-Id: I0015307bb02dfb9c60380b56d2a820f12169ebea Reviewed-on: https://gem5-review.googlesource.com/5381 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-17scons: Stop generating inc.d in the isa parser.Gabe Black
Generating dependency/build product information in the isa parser breaks scons idea of how a build is supposed to work. Arm twisting it into working forced a lot of false dependencies which slowed down the build. Change-Id: Iadee8c930fd7c80136d200d69870df7672a6b3ca Reviewed-on: https://gem5-review.googlesource.com/5081 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-10-13mem: Signal the local monitor when clearing the global monitorNikos Nikoleris
ARM systems require the coordination of the global and local monitors. When the system is run without caches the global monitor is implemented in the abstract memory object. This change adds a callback from the abstract memory that notifies the local monitor when the global monitor is cleared. Additionally, for ARM systems the local monitor signals the event register and wakes the thread context up. Subsequent wait-for-event (WFE) instructions will be immediately signaled. Change-Id: If6c038f3a6bea7239ba4258f07f39c7f9a30500b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3760 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-09-11stats: Get rid of some kernel stats related cruft.Gabe Black
The kernel stat mechanism should really be refactored and moved somewhere else, but in the mean time there's some old cruft that can be cleared away. Change-Id: I21e725de590dda0d20bf3bc675bbe976c7b1bd86 Reviewed-on: https://gem5-review.googlesource.com/4600 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-17riscv: Define register index constants using literalsAlec Roelke
To make it clearer what the register indices are for the semantically meaningful registers defined by src/arch/riscv/registers.hh, the constants that were defined using other constants were changed to use the literal values of those constants. This also removes the need to use the M5_VAR_USED attribute. Change-Id: I7cccbe45d3d820deb5149a5925415735f6ae2e61 Reviewed-on: https://gem5-review.googlesource.com/4080 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-07-14riscv: Disambiguate between the C and C++ versions of isnan and isinf.Gabe Black
When both the C and C++ versions are visible, the compiler will complain that it doesn't know which one to use. By specifying the std namespace, it will know to use the C++ version. Change-Id: Ie1bbe1d95eadbad9644b4915c21f924d7d5c0b22 Reviewed-on: https://gem5-review.googlesource.com/4060 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-07-14riscv: Fix bugs with RISC-V decoder and detailed CPUsAlec Roelke
This patch fixes some bugs that were missed with the changes to the decoder that enabled compatibility with compressed instructions. In order to accommodate speculation with variable instruction widths, a few assertions in decoder had to be changed to returning faults as the specification describes should normally happen. The rest of these assertions will be changed in a later patch. [Remove commented-out debugging line and add clarifying comment to registerName in utility.hh.] Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95 Reviewed-on: https://gem5-review.googlesource.com/4041 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-07-14riscv: Add unused attribute to some registers.hh constantsAlec Roelke
Three of the constants defined in arch/riscv/registers.hh (ReturnValueReg, SyscallNumReg, and SyscallPseudoReturnReg) may cause the compiler to warn that they are unused, which results in an error. This patch adds M5_VAR_USED attributes to them to stop this. Change-Id: Ie6389a55e8ffb3d003a47d02e76bdf9fb5219457 Reviewed-on: https://gem5-review.googlesource.com/4040 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-07-11arch-riscv: Add support for compressed extension RV64CAlec Roelke
This patch adds compatibility with the 64-bit compressed extension to the RISC-V ISA, RV64C. Current versions of the toolchain may use compressed instructions in glibc by default, which can only be overridden by recompiling the entire toolchain (simply adding "-march=rv64g" or "-march=rv64imafd" when compiling a binary is not sufficient to use uncompressed instructions in glibc functions in the binary). [Update diassembly generation for new RegId type.] [Rebase onto master.] Change-Id: Ifd5a5ea746704ce7e1b111442c3eb84c509a98b4 Reviewed-on: https://gem5-review.googlesource.com/3860 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-07-11arch-riscv: Restructure ISA descriptionAlec Roelke
This patch restructures the RISC-V ISA description to use fewer classes and improve its ability to be extended with nonstandard extensions in the future. It also cleans up the disassembly for some of the CSR and system instructions by removing source and destination registers for instructions that don't have any. [Fix class UImmOp to have an "imm" member rather than "uimm".] [Update disassembly generation for new RegId class.] Change-Id: Iec1c782020126e5e8e73460b84e31c7b5a5971d9 Reviewed-on: https://gem5-review.googlesource.com/3800 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
This patch adds some more functionality to the cpu model and the arch to interface with the vector register file. This change consists mainly of augmenting ThreadContexts and ExecContexts with calls to get/set full vectors, underlying microarchitectural elements or lanes. Those are meant to interface with the vector register file. All classes that implement this interface also get an appropriate implementation. This requires implementing the vector register file for the different models using the VecRegContainer class. This change set also updates the Result abstraction to contemplate the possibility of having a vector as result. The changes also affect how the remote_gdb connection works. There are some (nasty) side effects, such as the need to define dummy numPhysVecRegs parameter values for architectures that do not implement vector extensions. Nathanael Premillieu's work with an increasing number of fixes and improvements of mine. Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues and CC reg free list initialisation ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2705
2017-07-05cpu: Simplify the rename interface and use RegIdRekai Gonzalez-Alberquilla
With the hierarchical RegId there are a lot of functions that are redundant now. The idea behind the simplification is that instead of having the regId, telling which kind of register read/write/rename/lookup/etc. and then the function panic_if'ing if the regId is not of the appropriate type, we provide an interface that decides what kind of register to read depending on the register type of the given regId. Change-Id: I7d52e9e21fc01205ae365d86921a4ceb67a57178 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2702
2017-07-05arch, cpu: Architectural Register structural indexingNathanael Premillieu
Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700
2017-05-23arch-riscv: Fix bad stack initializationAlec Roelke
This patch fixes a problem with RISC-V initial stack setup in SE mode where the AT_RANDOM aux vector value contains an address that is too close to the top of the stack and doesn't fit the required 16 bytes. To fix this, the program header table was added to the top of the stack just like the RISC-V proxy kernel does. Change-Id: I814562e060ff041cd0d7a7c54c3685645bd325a3 Reviewed-on: https://gem5-review.googlesource.com/3401 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-05-18base: Refactor the GDB code.Gabe Black
The new version modularizes the implementation of the various commands, gets rid of dynamic allocation of the register cache, fixes some small style problems, and uses exceptions to simplify error handling internal to the GDB stub. Change-Id: Iff3548373ce4adfb99106a810f5713b769df89b2 Reviewed-on: https://gem5-review.googlesource.com/3280 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Boris Shingarov <shingarov@gmail.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-18syscall_emul, riscv: add override keyword to RISCV Process classBrandon Potter
Change-Id: I2a146ae57aac3787389997961208474a97e7c155 Reviewed-on: https://gem5-review.googlesource.com/3360 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-04-11riscv: Fix crashes with large or frequent mmapsAlec Roelke
This patch fixes a bug where increasing the mmap region too much causes it to run into already-allocated memory, which causes gem5 to fail an assertion. Previously, the stack was incorrectly set up such that the end of the mmap region and the top of the stack were the same address and both would grow downward. With this patch, the top of the stack has been separated from the end of mmap and moved up, and the mmap region now grows upward instead of downward. [Rebase to master branch and remove dependencies.] Change-Id: I7271ff478fff2994f918bc5003a6139b9ba6a520 Reviewed-on: https://gem5-review.googlesource.com/2680 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05riscv: fix Linux problems with LR and SC opsAlec Roelke
Some of the functions in the Linux toolchain that allocate memory make use of paired LR and SC instructions, which didn't work properly for that toolchain. This patch fixes that so attempting to use those functions doesn't cause an endless loop of failed SC instructions. Change-Id: If27696323dd6229a0277818e3744fbdf7180fca7 Reviewed-on: https://gem5-review.googlesource.com/2340 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05riscv: fix compatibility with Linux toolchainAlec Roelke
Previously, RISC-V in gem5 only supported RISC-V's Newlib toolchain (riscv64-unknown-elf-*) due to incorrect assumptions made in the initial setup of the user stack in SE mode. This patch fixes that by referring to the RISC-V proxy kernel code (https://github.com/riscv/riscv-pk) and setting up the stack according to how it does it. Now binaries compiled using the Linux toolchain (riscv64-unknown-linux-gnu-*) will run as well. [Update for recent changes to MemState to add accessors and mutators to get its members.] Change-Id: I6d2c486df7688efe3df54273e9aa0fd686851285 Reviewed-on: https://gem5-review.googlesource.com/2305 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05riscv: add remote gdb supportAlec Roelke
This patch adds support for debugging with remote GDB to RISC-V. Using GDB compiled with the RISC-V GNU toolchain, it is possible to pause and continue execution, view debugging information, etc. As with the rest of RISC-V, this does not support full-system mode. Change-Id: I2d3a8be614725e1be4b4c283f9fb678a0a30578d Reviewed-on: https://gem5-review.googlesource.com/2304 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05riscv: fix error on memory op address overflowAlec Roelke
Previously, if a memory operation referenced an address that caused the data to wrap around to the beginning of the memory (such as -1 or 0xFFFFFFFFFFFFFFFF), an assert would fail during address translation and gem5 would crash. This patch fixes that by checking for such a case in RISC-V's TLB code and returning a fault from translateData if that would happen. Because RISC-V does support unaligned memory accesses, no checking is performed to make sure that an access doesn't cross a cache line. [Update creation of page table fault to use make_shared.] [Add comment explaining the change and assertion that the memory request isn't zero size.] Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410 Reviewed-on: https://gem5-review.googlesource.com/2345 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05riscv: enable unaligned memory accessesAlec Roelke
Sometimes an ld instruction will be split across a cache boundary. Previously RISC-V was set to not allow this. This patch fixes that. Change-Id: I8bc8ea6d67f65a9b3662e14c4037f4224799d20f Reviewed-on: https://gem5-review.googlesource.com/2341 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-03-09syscall-emul: Rewrite system call exit codeBrandon Potter
The changeset does a major refactor on the exit, exit_group, and futex system calls regarding exit functionality. A FutexMap class and related structures are added into a new file. This increases code clarity by encapsulating the futex operations and the futex state into an object. Several exit conditions were added to allow the simulator to end processes under certain conditions. Also, the simulation only exits now when all processes have finished executing. Change-Id: I1ee244caa9b5586fe7375e5b9b50fd3959b9655e Reviewed-on: https://gem5-review.googlesource.com/2269 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-03-09syscall-emul: Move memState into its own fileBrandon Potter
The Process class is full of implementation details and structures related to SE Mode. This changeset factors out an internal class from Process and moves it into a separate file. The purpose behind doing this is to clean up the code and make it a bit more modular. Change-Id: Ic6941a1657751e8d51d5b6b1dcc04f1195884280 Reviewed-on: https://gem5-review.googlesource.com/2263 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-02-27syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess ↵Brandon Potter
simulations Modifies the clone system call and adds execve system call. Requires allowing processes to steal thread contexts from other processes in the same system object and the ability to detach pieces of process state (such as MemState) to allow dynamic sharing.
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