summaryrefslogtreecommitdiff
path: root/src/arch/riscv
AgeCommit message (Expand)Author
2018-01-05arch-riscv: Correct syscall argument reg countAlec Roelke
2018-01-04arch-riscv: Remove "magic" syscall number constantAlec Roelke
2017-12-23alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst.Gabe Black
2017-12-23riscv,x86: Stop using the arch Nop machine instruction unnecessarily.Gabe Black
2017-12-22arch,cpu: "virtualize" the TLB interface.Gabe Black
2017-12-14arch-riscv: Define AT_RANDOM properlyAlec Roelke
2017-12-14arch-riscv: Increase maximum stack sizeAlec Roelke
2017-12-13cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.Gabe Black
2017-12-07arch-riscv: Move compressed ops out of ISAAlec Roelke
2017-12-04misc: Rename misc.(hh|cc) to logging.(hh|cc)Gabe Black
2017-11-30arch-riscv: use sext rather than manual masksAlec Roelke
2017-11-30arch-riscv: Remove spaces around ea_codeAlec Roelke
2017-11-29arch-riscv: Add missing license paragraphsAlec Roelke
2017-11-29arch-riscv: Remove static parts of AMOs out of ISAAlec Roelke
2017-11-29arch-riscv: Move parts of mem insts out of ISAAlec Roelke
2017-11-29arch-riscv: Move unknown out of ISA descriptionAlec Roelke
2017-11-29arch-riscv: Move standard ops out of ISAAlec Roelke
2017-11-28arch-riscv: Move static_inst into a directoryAlec Roelke
2017-11-22arch-riscv: Add missing system callsAlec Roelke
2017-11-07alpha,arm,mips,power,riscv,sparc,x86: Merge exec decl templates.Gabe Black
2017-11-02alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts.Gabe Black
2017-10-17scons: Stop generating inc.d in the isa parser.Gabe Black
2017-10-13mem: Signal the local monitor when clearing the global monitorNikos Nikoleris
2017-09-11stats: Get rid of some kernel stats related cruft.Gabe Black
2017-07-17riscv: Define register index constants using literalsAlec Roelke
2017-07-14riscv: Disambiguate between the C and C++ versions of isnan and isinf.Gabe Black
2017-07-14riscv: Fix bugs with RISC-V decoder and detailed CPUsAlec Roelke
2017-07-14riscv: Add unused attribute to some registers.hh constantsAlec Roelke
2017-07-11arch-riscv: Add support for compressed extension RV64CAlec Roelke
2017-07-11arch-riscv: Restructure ISA descriptionAlec Roelke
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
2017-07-05cpu: Simplify the rename interface and use RegIdRekai Gonzalez-Alberquilla
2017-07-05arch, cpu: Architectural Register structural indexingNathanael Premillieu
2017-05-23arch-riscv: Fix bad stack initializationAlec Roelke
2017-05-18base: Refactor the GDB code.Gabe Black
2017-05-18syscall_emul, riscv: add override keyword to RISCV Process classBrandon Potter
2017-04-11riscv: Fix crashes with large or frequent mmapsAlec Roelke
2017-04-05riscv: fix Linux problems with LR and SC opsAlec Roelke
2017-04-05riscv: fix compatibility with Linux toolchainAlec Roelke
2017-04-05riscv: add remote gdb supportAlec Roelke
2017-04-05riscv: fix error on memory op address overflowAlec Roelke
2017-04-05riscv: enable unaligned memory accessesAlec Roelke
2017-03-09syscall-emul: Rewrite system call exit codeBrandon Potter
2017-03-09syscall-emul: Move memState into its own fileBrandon Potter
2017-02-27syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess s...Brandon Potter
2015-07-20syscall_emul: [patch 13/22] add system call retry capabilityBrandon Potter
2016-11-09syscall_emul: [patch 8/22] refactor process classBrandon Potter
2016-11-09syscall_emul: [patch 5/22] remove LiveProcess class and use Process insteadBrandon Potter
2017-01-27riscv: Fix crash when syscall argument reg index is too highAlec Roelke
2016-11-09style: [patch 3/22] reduce include dependencies in some headersBrandon Potter