| Age | Commit message (Expand) | Author |
|---|
| 2018-01-20 | arch, mem: Make the page table lookup function return a pointer. | Gabe Black |
| 2018-01-20 | sim, arch, base: Refactor the base remote GDB class. | Gabe Black |
| 2018-01-19 | arch, mem, sim: Consolidate and rename the SE mode page table classes. | Gabe Black |
| 2018-01-16 | arch-riscv: Fix floating-poing op classes | Alec Roelke |
| 2018-01-16 | arch-riscv: Fix floating-point conversion bugs | Alec Roelke |
| 2018-01-15 | arch: Fix a fatal_if in most of the arch's process classes. | Gabe Black |
| 2018-01-11 | arch-riscv: Don't crash when printing unknown CSRs | Alec Roelke |
| 2018-01-11 | arch,mem: Remove the default value for page size. | Gabe Black |
| 2018-01-11 | arch,mem: Move page table construction into the arch classes. | Gabe Black |
| 2018-01-10 | arch-riscv: Make use of ImmOp's polymorphism | Alec Roelke |
| 2018-01-10 | alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT. | Gabe Black |
| 2018-01-05 | arch-riscv: Ignore sched_yield syscall in SE mode | Tuan Ta |
| 2018-01-05 | arch-riscv: Ignore set_robust_list and get_robust_list syscalls | Tuan Ta |
| 2018-01-05 | arch-riscv: Add an implementation of set_tid_address syscall in RISCV | Tuan Ta |
| 2018-01-05 | arch-riscv: Correct syscall argument reg count | Alec Roelke |
| 2018-01-04 | arch-riscv: Remove "magic" syscall number constant | Alec Roelke |
| 2017-12-23 | alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst. | Gabe Black |
| 2017-12-23 | riscv,x86: Stop using the arch Nop machine instruction unnecessarily. | Gabe Black |
| 2017-12-22 | arch,cpu: "virtualize" the TLB interface. | Gabe Black |
| 2017-12-14 | arch-riscv: Define AT_RANDOM properly | Alec Roelke |
| 2017-12-14 | arch-riscv: Increase maximum stack size | Alec Roelke |
| 2017-12-13 | cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst. | Gabe Black |
| 2017-12-07 | arch-riscv: Move compressed ops out of ISA | Alec Roelke |
| 2017-12-04 | misc: Rename misc.(hh|cc) to logging.(hh|cc) | Gabe Black |
| 2017-11-30 | arch-riscv: use sext rather than manual masks | Alec Roelke |
| 2017-11-30 | arch-riscv: Remove spaces around ea_code | Alec Roelke |
| 2017-11-29 | arch-riscv: Add missing license paragraphs | Alec Roelke |
| 2017-11-29 | arch-riscv: Remove static parts of AMOs out of ISA | Alec Roelke |
| 2017-11-29 | arch-riscv: Move parts of mem insts out of ISA | Alec Roelke |
| 2017-11-29 | arch-riscv: Move unknown out of ISA description | Alec Roelke |
| 2017-11-29 | arch-riscv: Move standard ops out of ISA | Alec Roelke |
| 2017-11-28 | arch-riscv: Move static_inst into a directory | Alec Roelke |
| 2017-11-22 | arch-riscv: Add missing system calls | Alec Roelke |
| 2017-11-07 | alpha,arm,mips,power,riscv,sparc,x86: Merge exec decl templates. | Gabe Black |
| 2017-11-02 | alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts. | Gabe Black |
| 2017-10-17 | scons: Stop generating inc.d in the isa parser. | Gabe Black |
| 2017-10-13 | mem: Signal the local monitor when clearing the global monitor | Nikos Nikoleris |
| 2017-09-11 | stats: Get rid of some kernel stats related cruft. | Gabe Black |
| 2017-07-17 | riscv: Define register index constants using literals | Alec Roelke |
| 2017-07-14 | riscv: Disambiguate between the C and C++ versions of isnan and isinf. | Gabe Black |
| 2017-07-14 | riscv: Fix bugs with RISC-V decoder and detailed CPUs | Alec Roelke |
| 2017-07-14 | riscv: Add unused attribute to some registers.hh constants | Alec Roelke |
| 2017-07-11 | arch-riscv: Add support for compressed extension RV64C | Alec Roelke |
| 2017-07-11 | arch-riscv: Restructure ISA description | Alec Roelke |
| 2017-07-05 | cpu: Added interface for vector reg file | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | cpu: Simplify the rename interface and use RegId | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | arch, cpu: Architectural Register structural indexing | Nathanael Premillieu |
| 2017-05-23 | arch-riscv: Fix bad stack initialization | Alec Roelke |
| 2017-05-18 | base: Refactor the GDB code. | Gabe Black |
| 2017-05-18 | syscall_emul, riscv: add override keyword to RISCV Process class | Brandon Potter |
