| Age | Commit message (Expand) | Author |
|---|
| 2018-09-19 | syscall_emul: expand AuxVector class | Brandon Potter |
| 2018-07-28 | arch-riscv: Add xret instructions | Alec Roelke |
| 2018-07-28 | arch-riscv: Add support for trap value register | Alec Roelke |
| 2018-07-28 | arch-riscv: Add support for fault handling | Alec Roelke |
| 2018-07-09 | arch-riscv: enable rudimentary fs simulation | Robert |
| 2018-07-09 | arch-riscv: Fix the srlw and srliw instructions. | Austin Harris |
| 2018-06-11 | misc: Using smart pointers for memory Requests | Giacomo Travaglini |
| 2018-06-11 | misc: Substitute pointer to Request with aliased RequestPtr | Giacomo Travaglini |
| 2018-05-12 | arch-riscv: Update CSR implementations | Alec Roelke |
| 2018-03-27 | arch: cpu: Make the ExtMachInst type a template argument in InstMap. | Gabe Black |
| 2018-03-26 | arch: Fix all override related warnings. | Gabe Black |
| 2018-03-26 | arch: Add a virtual asBytes function to the StaticInst class. | Gabe Black |
| 2018-03-20 | riscv: throw IllegalInstFault when decoding invalid instructions | Tuan Ta |
| 2018-02-19 | arch-riscv: Fix compressed branch op offset | Alec Roelke |
| 2018-01-29 | riscv: Add overrides to various StaticInst methods. | Gabe Black |
| 2018-01-20 | arch, mem: Make the page table lookup function return a pointer. | Gabe Black |
| 2018-01-20 | sim, arch, base: Refactor the base remote GDB class. | Gabe Black |
| 2018-01-19 | arch, mem, sim: Consolidate and rename the SE mode page table classes. | Gabe Black |
| 2018-01-16 | arch-riscv: Fix floating-poing op classes | Alec Roelke |
| 2018-01-16 | arch-riscv: Fix floating-point conversion bugs | Alec Roelke |
| 2018-01-15 | arch: Fix a fatal_if in most of the arch's process classes. | Gabe Black |
| 2018-01-11 | arch-riscv: Don't crash when printing unknown CSRs | Alec Roelke |
| 2018-01-11 | arch,mem: Remove the default value for page size. | Gabe Black |
| 2018-01-11 | arch,mem: Move page table construction into the arch classes. | Gabe Black |
| 2018-01-10 | arch-riscv: Make use of ImmOp's polymorphism | Alec Roelke |
| 2018-01-10 | alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT. | Gabe Black |
| 2018-01-05 | arch-riscv: Ignore sched_yield syscall in SE mode | Tuan Ta |
| 2018-01-05 | arch-riscv: Ignore set_robust_list and get_robust_list syscalls | Tuan Ta |
| 2018-01-05 | arch-riscv: Add an implementation of set_tid_address syscall in RISCV | Tuan Ta |
| 2018-01-05 | arch-riscv: Correct syscall argument reg count | Alec Roelke |
| 2018-01-04 | arch-riscv: Remove "magic" syscall number constant | Alec Roelke |
| 2017-12-23 | alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst. | Gabe Black |
| 2017-12-23 | riscv,x86: Stop using the arch Nop machine instruction unnecessarily. | Gabe Black |
| 2017-12-22 | arch,cpu: "virtualize" the TLB interface. | Gabe Black |
| 2017-12-14 | arch-riscv: Define AT_RANDOM properly | Alec Roelke |
| 2017-12-14 | arch-riscv: Increase maximum stack size | Alec Roelke |
| 2017-12-13 | cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst. | Gabe Black |
| 2017-12-07 | arch-riscv: Move compressed ops out of ISA | Alec Roelke |
| 2017-12-04 | misc: Rename misc.(hh|cc) to logging.(hh|cc) | Gabe Black |
| 2017-11-30 | arch-riscv: use sext rather than manual masks | Alec Roelke |
| 2017-11-30 | arch-riscv: Remove spaces around ea_code | Alec Roelke |
| 2017-11-29 | arch-riscv: Add missing license paragraphs | Alec Roelke |
| 2017-11-29 | arch-riscv: Remove static parts of AMOs out of ISA | Alec Roelke |
| 2017-11-29 | arch-riscv: Move parts of mem insts out of ISA | Alec Roelke |
| 2017-11-29 | arch-riscv: Move unknown out of ISA description | Alec Roelke |
| 2017-11-29 | arch-riscv: Move standard ops out of ISA | Alec Roelke |
| 2017-11-28 | arch-riscv: Move static_inst into a directory | Alec Roelke |
| 2017-11-22 | arch-riscv: Add missing system calls | Alec Roelke |
| 2017-11-07 | alpha,arm,mips,power,riscv,sparc,x86: Merge exec decl templates. | Gabe Black |
| 2017-11-02 | alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts. | Gabe Black |
