| Age | Commit message (Expand) | Author |
|---|
| 2019-11-02 | arch,cpu: Move endianness conversion of inst bytes into the ISA. | Gabe Black |
| 2019-10-30 | arch: Make endianness a property of the OS class syscalls can consume. | Gabe Black |
| 2019-10-25 | mips,riscv: Get rid of some Alpha cruft in these System classes. | Gabe Black |
| 2019-10-25 | cpu: Create a PCEventScope class to abstract the scope of PCEvents. | Gabe Black |
| 2019-10-19 | arch: Make a base class for Interrupts. | Gabe Black |
| 2019-10-16 | arch,base,sim: Move Process loader hooks into the Process class. | Gabe Black |
| 2019-10-12 | arch,base: Separate the idea of a memory image and object file. | Gabe Black |
| 2019-10-10 | arch,base: Stop loading the interpreter in ElfObject. | Gabe Black |
| 2019-10-10 | arch, base: Stop assuming object files have three segments. | Gabe Black |
| 2019-10-09 | arch-mips,arch-riscv,base: Get rid of the unused HexFile class. | Gabe Black |
| 2019-10-09 | base: Rename Section to Segment, and some of its members. | Gabe Black |
| 2019-08-23 | arch-riscv: fix GDB register cache | Alec Roelke |
| 2019-08-21 | arch-riscv: Update register file | Yifei Liu |
| 2019-05-30 | arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy. | Gabe Black |
| 2019-05-29 | sim-se: add a release parameter to Process.py | Ciro Santilli |
| 2019-05-21 | sim-se: change syscall function signature | Brandon Potter |
| 2019-05-20 | riscv: Add an object file loader for linux. | Gabe Black |
| 2019-05-04 | arch-riscv: Implement MHARTID CSR | Alec Roelke |
| 2019-05-03 | arch-riscv,isa: Fix for compressed jump (c_j) imm | Avishai Tvila |
| 2019-04-30 | arch: Stop using TheISA within the ISAs. | Gabe Black |
| 2019-04-28 | arch, sim: Simplify the AuxVector type. | Gabe Black |
| 2019-02-12 | python: Don't assume SimObjects live in the global namespace | Andreas Sandberg |
| 2019-02-08 | riscv: fix AMO, LR and SC instructions | Tuan Ta |
| 2019-02-08 | riscv: fixed syscall return value | Tuan Ta |
| 2019-02-08 | riscv: ignore nanosleep syscall | Tuan Ta |
| 2019-02-08 | arch-riscv: initialize RISC-V's thread pointer register in clone syscall | Tuan Ta |
| 2019-02-07 | arch-riscv: Enable support for riscv 32-bit in SE mode. | Austin Harris |
| 2019-02-06 | riscv: remove NonSpeculative flag from fence inst | Tuan Ta |
| 2019-02-06 | arch-riscv: Initialize interrupt mask | Tuan Ta |
| 2019-02-05 | misc: added missing override specifier | Andrea Mondelli |
| 2019-02-05 | riscv: Get rid of ISA specific register types in Interrupts. | Austin Harris |
| 2019-02-01 | cpu, arch: Replace the CCReg type with RegVal. | Gabe Black |
| 2019-01-31 | riscv: Get rid of some ISA specific register types. | Gabe Black |
| 2019-01-31 | arch: cpu: Rename *FloatRegBits* to *FloatReg*. | Gabe Black |
| 2019-01-30 | arch,cpu: Add vector predicate registers | Giacomo Gabrielli |
| 2019-01-24 | base: arch: Get rid of the now unused FloatRegVal type. | Gabe Black |
| 2019-01-22 | arch: cpu: Stop passing around misc registers by reference. | Gabe Black |
| 2019-01-22 | sim-se: add syscalls related to polling | Brandon Potter |
| 2019-01-16 | arch: Make the ISA register types aliases for the global types. | Gabe Black |
| 2019-01-16 | arch-riscv: Add interrupt handling | Alec Roelke |
| 2019-01-16 | arch-riscv: Fix reset function and style | Alec Roelke |
| 2019-01-10 | sim-se: Refactor clone to avoid most ifdefs | Andreas Sandberg |
| 2018-09-19 | syscall_emul: expand AuxVector class | Brandon Potter |
| 2018-07-28 | arch-riscv: Add xret instructions | Alec Roelke |
| 2018-07-28 | arch-riscv: Add support for trap value register | Alec Roelke |
| 2018-07-28 | arch-riscv: Add support for fault handling | Alec Roelke |
| 2018-07-09 | arch-riscv: enable rudimentary fs simulation | Robert |
| 2018-07-09 | arch-riscv: Fix the srlw and srliw instructions. | Austin Harris |
| 2018-06-11 | misc: Using smart pointers for memory Requests | Giacomo Travaglini |
| 2018-06-11 | misc: Substitute pointer to Request with aliased RequestPtr | Giacomo Travaglini |
