| Age | Commit message (Expand) | Author |
|---|---|---|
| 2007-03-07 | *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg | Ali Saidi |
| 2007-03-03 | Implement Niagara I/O interface and rework interrupts | Ali Saidi |
| 2007-02-06 | merge my index fix and lisa's fix | Ali Saidi |
| 2007-02-02 | make interrupt code serialize itself and fix indenting | Ali Saidi |
| 2007-02-01 | only increment numPosted if an interrupt of that type hasn't been posted before. | Lisa Hsu |
| 2007-01-19 | some hstick and hintp changes. | Lisa Hsu |
| 2007-01-11 | Add Trap Level Zero to interrupts, remove some unreachable code that I forgot... | Lisa Hsu |
| 2007-01-08 | the way i understand it, interrupts in m5 is a little bloated. the usage of ... | Lisa Hsu |
| 2006-12-08 | mostly implemented SOFTINT relevant interrupt stuff. | Lisa Hsu |
| 2006-11-14 | interrupts.hh: | Lisa Hsu |
| 2006-11-06 | Stub for SPARC interrupt handling object. | Gabe Black |
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