gem5 - gem5

Age	Commit message (Collapse)	Author
2007-01-19	some hstick and hintp changes.	Lisa Hsu
	src/arch/sparc/interrupts.hh: condition hstick matches on HINTP src/arch/sparc/miscregfile.cc: implement HINTP src/arch/sparc/ua2005.cc: don't post interrupt unless it is enabled. --HG-- extra : convert_revision : f71d1c1d9fd1a898ddafd5a885c3a8d5c75e8ff0
2007-01-11	Add Trap Level Zero to interrupts, remove some unreachable code that I ↵	Lisa Hsu
	forgot to remove last time. --HG-- extra : convert_revision : 74c4c4591be5a66c21077a6fc5f3f60b0ee9bcc1
2007-01-08	the way i understand it, interrupts in m5 is a little bloated. the usage of ↵	Lisa Hsu
	CPU->checkInterrupts bool is inconsistent, and i think should eventually be phased out. For now, I've just assumed that CPU->checkInterrupts() is the way to fast path a CPU if you have no interrupts by having a simple bitfield in each ISA to determine whether interrupts are pending. getInterrupts has been mostly filled in. src/arch/sparc/interrupts.hh: fill in how we do interrupts on sparc a little bit. 1) create a bitfield for interrupts, and check that in checkInterrupts() to fast path CPU. 2) fill in getInterrupts() a little bit. also, update the bitfield access to be HPSTATE::hpriv, etc. src/arch/sparc/ua2005.cc: 1) update formatting 2) change the way interrupts are done to use the new way to tickle the CPU. src/cpu/base.cc: src/cpu/base.hh: overload the post_interrupt function for SPARC interrupts - which are only denoted by a single int value. --HG-- extra : convert_revision : 9074a003eff37a40dcce78f56d20f6cbcc453eb5
2006-12-08	mostly implemented SOFTINT relevant interrupt stuff.	Lisa Hsu
	src/arch/sparc/interrupts.hh: add in thread_context.hh to get access to tc. get rid of stubs that don't make sense right now. implement checking and get softint interrupts src/arch/sparc/miscregfile.cc: softint should be OR-ed on a write. src/arch/sparc/miscregfile.hh: add some enums for state fields for easy access to bitmasks of HPSTATE and PSTATE regs. src/arch/sparc/ua2005.cc: implement writing SOFTINT, PSTATE, PIL, and HPSTATE properly, add helpful info to panic for bad reg write. --HG-- extra : convert_revision : d12d1147b508121075ee9be4599693554d4b9eae
2006-11-14	interrupts.hh:	Lisa Hsu
	make a likewise updateIntrInfo for Sparc that's blank so it doesn't fart on build src/arch/sparc/interrupts.hh: make a likewise updateIntrInfo for Sparc that's blank so it doesn't fart on build --HG-- extra : convert_revision : 5f469d0cf897479b42703104cd801a8ef923fcae
2006-11-06	Stub for SPARC interrupt handling object.	Gabe Black
	--HG-- extra : convert_revision : 7257e3387c01e84e5a1018a9cdcc09a79edfa934