| Age | Commit message (Expand) | Author |
|---|
| 2016-07-21 | isa: Modify get/check interrupt routines | Mitch Hayenga |
| 2015-10-12 | misc: Remove redundant compiler-specific defines | Andreas Hansson |
| 2015-07-07 | sim: Refactor the serialization base class | Andreas Sandberg |
| 2014-10-16 | arch: Use shared_ptr for all Faults | Andreas Hansson |
| 2012-02-11 | SPARC: Make PSTATE and HPSTATE a BitUnion. | Gabe Black |
| 2011-04-15 | trace: reimplement the DTRACE function so it doesn't use a vector | Nathan Binkert |
| 2010-11-11 | SPARC: Clean up some historical style issues. | Gabe Black |
| 2009-07-09 | SPARC: Fold the MiscRegFile all the way into the ISA object. | Gabe Black |
| 2009-07-08 | SPARC: Phase out SPARC's intregfile.hh. | Gabe Black |
| 2009-01-25 | CPU: Add a setCPU function to the interrupt objects. | Gabe Black |
| 2008-10-21 | style: Use the correct m5 style for things relating to interrupts. | Nathan Binkert |
| 2008-10-12 | Turn Interrupts objects into SimObjects. Also, move local APIC state into x86... | Gabe Black |
| 2007-03-07 | *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg | Ali Saidi |
| 2007-03-03 | Implement Niagara I/O interface and rework interrupts | Ali Saidi |
| 2007-02-06 | merge my index fix and lisa's fix | Ali Saidi |
| 2007-02-02 | make interrupt code serialize itself and fix indenting | Ali Saidi |
| 2007-02-01 | only increment numPosted if an interrupt of that type hasn't been posted before. | Lisa Hsu |
| 2007-01-19 | some hstick and hintp changes. | Lisa Hsu |
| 2007-01-11 | Add Trap Level Zero to interrupts, remove some unreachable code that I forgot... | Lisa Hsu |
| 2007-01-08 | the way i understand it, interrupts in m5 is a little bloated. the usage of ... | Lisa Hsu |
| 2006-12-08 | mostly implemented SOFTINT relevant interrupt stuff. | Lisa Hsu |
| 2006-11-14 | interrupts.hh: | Lisa Hsu |
| 2006-11-06 | Stub for SPARC interrupt handling object. | Gabe Black |
