gem5 - gem5

Age	Commit message (Collapse)	Author
2013-01-07	arch: Move the ISA object to a separate section	Andreas Sandberg
	After making the ISA an independent SimObject, it is serialized automatically by the Python world. Previously, this just resulted in an empty ISA section. This patch moves the contents of the ISA to that section and removes the explicit ISA serialization from the thread contexts, which makes it behave like a normal SimObject during serialization. Note: This patch breaks checkpoint backwards compatibility! Use the cpt_upgrader.py utility to upgrade old checkpoints to the new format.
2013-01-07	arch: Make the ISA class inherit from SimObject	Andreas Sandberg
	The ISA class on stores the contents of ID registers on many architectures. In order to make reset values of such registers configurable, we make the class inherit from SimObject, which allows us to use the normal generated parameter headers. This patch introduces a Python helper method, BaseCPU.createThreads(), which creates a set of ISAs for each of the threads in an SMT system. Although it is currently only needed when creating multi-threaded CPUs, it should always be called before instantiating the system as this is an obvious place to configure ID registers identifying a thread/CPU.
2013-01-04	Decoder: Remove the thread context get/set from the decoder.	Gabe Black
	This interface is no longer used, and getting rid of it simplifies the decoders and code that sets up the decoders. The thread context had been used to read architectural state which was used to contextualize the instruction memory as it came in. That was changed so that the state is now sent to the decoders to keep locally if/when it changes. That's significantly more efficient. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-01-04	SPARC: Keep a copy of the current ASI in the decoder.	Gabe Black
	Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2012-02-11	SPARC: Make PSTATE and HPSTATE a BitUnion.	Gabe Black
	This gets rid of cryptic bits of code with lots of bit manipulation, and makes some comments redundant.
2011-11-18	SE/FS: Get rid of includes of config/full_system.hh.	Gabe Black

2011-10-09	[mq]: sefssparcregfile.patch	Gabe Black

2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
	At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help
2010-11-11	SPARC: Clean up some historical style issues.	Gabe Black

2010-10-10	SPARC: Make SPARC's ISA's clear function initialize everything it should.	Gabe Black
	Also make it not set some pointers to NULL potentially introducing a memory leak. That should be done in the constructor.
2009-07-10	SPARC: Set up a lookup table for integer register flattening.	Gabe Black
	Using a look up table changed the run time of the SPARC_FS solaris boot regression from: real 14m45.951s user 13m57.528s sys 0m3.452s to: real 12m19.777s user 12m2.685s sys 0m2.420s
2009-07-09	SPARC: Fold the MiscRegFile all the way into the ISA object.	Gabe Black

2009-07-08	Registers: Add an ISA object which replaces the MiscRegFile.	Gabe Black
	This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.