gem5 - gem5

Age	Commit message (Expand)	Author
2007-04-22	Make the GSR into a renamed control register. It should be split into a renam...	Gabe Black
2007-04-14	Make the fsr a serializing register. Other control registers probably need th...	Gabe Black
2007-04-11	Create a filter and a union to translate the SPARC instruction implementation...	Gabe Black
2007-03-02	make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way a...	Ali Saidi
2007-02-24	make m5 readfile work on solaris... we can have a solaris regression soon!	Ali Saidi
2007-02-21	add pseduo instruction support for sparc	Ali Saidi
2007-02-12	rename store conditional stuff as extra data so it can be used for conditiona...	Ali Saidi
2007-01-29	Fix the Frs?s operands to use single width by default, rather than double width.	Gabe Black
2006-12-17	Merge zizzer:/bk/newmem	Gabe Black
2006-12-16	Support for twin loads.	Gabe Black
2006-12-16	Made changes to CWP be non speculative.	Gabe Black
2006-12-05	Move the SyscallReturn class into sim/syscallreturn.hh. Also move some miscre...	Gabe Black
2006-11-23	Fixes to the isa description.	Gabe Black
2006-11-10	Added StrandStsReg operand.	Gabe Black
2006-11-10	Fix up instructions to read and write control registers, and got rid of the c...	Gabe Black
2006-10-29	Add an integer microcode register.	Gabe Black
2006-10-25	Fixed the priv instruction format.	Gabe Black
2006-10-23	Broke Load/Store instructions into microcode, and partially refactored memory...	Gabe Black
2006-10-18	Zeroed out the actual LSB in addition to moving it's original value the MSB.	Gabe Black
2006-10-16	Changed how floating point register numbers are decoded to fit with the spec.	Gabe Black
2006-10-12	Some support for handling block loads and stores and ASIs properly.	Gabe Black
2006-07-26	Now ignore sigaction	Gabe Black
2006-07-22	Fixed subtract with carry, and started some work with floating point.	Gabe Black
2006-05-26	Implement PR/HPR/ASR for full system	Ali Saidi
2006-05-22	New directory structure:	Steve Reinhardt