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path: root/src/arch/sparc/isa
AgeCommit message (Expand)Author
2007-03-07*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscRegAli Saidi
2007-03-02make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way a...Ali Saidi
2007-02-28Make the m5 psuedo instructions use the BasicOperate formatGabe Black
2007-02-28Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2007-02-28Make trap instructions always generate TrapInstruction Fault objects which ca...Gabe Black
2007-02-24Merge zizzer:/bk/newmemAli Saidi
2007-02-24make m5 readfile work on solaris... we can have a solaris regression soon!Ali Saidi
2007-02-23Ali and I both made the same change and we only need it once. I liked mine a ...Gabe Black
2007-02-23Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2007-02-22Make the m5 pseudo instructions only work in FS. Also, make sure any undefine...Gabe Black
2007-02-22fix se compiling oopsAli Saidi
2007-02-21add pseduo instruction support for sparcAli Saidi
2007-02-12rename store conditional stuff as extra data so it can be used for conditiona...Ali Saidi
2007-02-06more fp fixesAli Saidi
2007-02-02more sparc fixesAli Saidi
2007-02-02fix mostly floating point relatedAli Saidi
2007-01-30Merge zizzer:/bk/newmemGabe Black
2007-01-30Implemented fbfss and fbpfcc instructions, and cleaned up branch code a little.Gabe Black
2007-01-30change std::isnan() to a using namespace std and isnan(). We need a better wa...Ali Saidi
2007-01-30use std:: for isnan() and fix decoding of fcmpe*Ali Saidi
2007-01-30Make the FpUnimpl format actually write the Fsr.Gabe Black
2007-01-30Added FpUnimpl format for quad precision and other purposefully unimplemented...Gabe Black
2007-01-29Fix the Frs?s operands to use single width by default, rather than double width.Gabe Black
2007-01-29Add implementation for the fcmp instructions. These don't behave -quite- righ...Gabe Black
2007-01-29Fix the FCMPCC bitfield.Gabe Black
2007-01-29Cleaned up disassembly a little.Gabe Black
2007-01-28Merge zizzer:/bk/newmemGabe Black
2007-01-28make unimplemented ops failAli Saidi
2007-01-27Merge zizzer:/bk/newmemGabe Black
2007-01-27Fixed up printReg so that control registers are printed by name. This is poss...Gabe Black
2007-01-26Merge zizzer:/bk/newmemAli Saidi
2007-01-26Make Sparc traceflag even more chattyAli Saidi
2007-01-26Merge zeep.pool:/z/saidi/work/m5.newmemAli Saidi
2007-01-26make our code a little more standards compliantAli Saidi
2007-01-25fix smul and sdiv to sign extend, and handle overflow/underflow corretlyAli Saidi
2007-01-24Merge zizzer:/bk/newmemGabe Black
2007-01-23use pstate.am to mask off PC/NPC where it needs to +beAli Saidi
2007-01-22Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2007-01-22clean up fault code a little bitAli Saidi
2007-01-20fix flushw implementationAli Saidi
2007-01-20Spill and Fill handlers are actually n*4 + the start addressAli Saidi
2007-01-16Modify ISA and staticInst to support a IsFirstMicroOp flagAli Saidi
2007-01-10bug fixes to get us to 145m instructionsAli Saidi
2007-01-03Merge zizzer:/bk/newmemGabe Black
2006-12-19fix twinx loads a little bitAli Saidi
2006-12-18Fixing the extended twin format to go with the new isa parser interface.Gabe Black
2006-12-18Merge zizzer.eecs.umich.edu:/.automount/zower/eecshome/m5/newmemGabe Black
2006-12-18move the twinx loads to the correct opcode and add asis 0x24 and 0x27Ali Saidi
2006-12-17Minor cleanup of new snippet/subst code.Steve Reinhardt
2006-12-17Merge zizzer:/bk/newmemGabe Black
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