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path: root/src/arch/sparc/isa
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2006-11-10fix endian issues with condition codesAli Saidi
use memcpy instead of bcopy s/u_int32_t/uint32_t/g fixup endian code to work with solaris hack to make sure htole() works... Nate, have a good idea to fix this? src/arch/sparc/faults.cc: set the reset address to be 40 bits. Makes PC printing easier at least for now. src/arch/sparc/isa/base.isa: fix endian issues with condition codes src/arch/sparc/tlb.hh: add implemented physical addres constants src/arch/sparc/utility.hh: add tlb.hh to utilities src/base/loader/raw_object.cc: add a symbol <filename>_start to the symbol table for binaries files src/base/remote_gdb.cc: use memcpy instead of bcopy src/cpu/exetrace.cc: clean up printing a bit more src/cpu/m5legion_interface.h: add tons to the shared interface src/dev/ethertap.cc: s/u_int32_t/uint32_t/g src/dev/ide_atareg.h: fixup endian code to work with solaris src/dev/pcidev.cc: src/sim/param.hh: hack to make sure htole() works... --HG-- extra : convert_revision : 4579392184b40bcc1062671a953c6595c685e9b2
2006-11-10Added StrandStsReg operand.Gabe Black
--HG-- extra : convert_revision : 51be41716ed9fe0e99e53f2341ad5651a525055a
2006-11-10Put in provisions for rd, rdpr, rdhpr, wr, wrpr, and wrhpr to disassemble ↵Gabe Black
properly. --HG-- extra : convert_revision : f2cad8a5879999438ba9b05f15a91320e7a4cc4a
2006-11-10Made the annul of unconditional conditional branches behave properly, added ↵Gabe Black
code to read and write the strand_sts_reg, and made restored a Priv instruction. --HG-- extra : convert_revision : 386512215f7243d230717c369217f8d2f9ada935
2006-11-10Fixed up the code that prints out registers to take into account microregisters.Gabe Black
--HG-- extra : convert_revision : 6809de467e4500ce34447c0544caf0ba04af81e7
2006-11-10Fix up instructions to read and write control registers, and got rid of the ↵Gabe Black
control register fields which won't work on a big endian host. --HG-- extra : convert_revision : 1b518873b6e1a073b58cbe27642537d5ae3a604d
2006-11-03Calling syscalls from within the trap instruction's invoke method won't work ↵Gabe Black
because apparently you need an xc for that and not a tc. Cleaned up the TrapInstruction fault in light of this. --HG-- extra : convert_revision : 1805c9244cfd62d0ee7862d8fd7c9983e00c5747
2006-11-03Add the syscall number as the second parameter for the trap fault. This ↵Gabe Black
could be improved and syscalls could be called from the trap's invoke method. --HG-- extra : convert_revision : 127a3673a076110fb3605c0fbc93e8d7e9fec84b
2006-11-01Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register ↵Gabe Black
file functions to not take faults --HG-- extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
2006-10-29Move the mem classes into util.isa so that multiple inheritance can be used ↵Gabe Black
in the future for micro insts. --HG-- extra : convert_revision : c71faa5e43b56ed15d00ed5fd57c020d1c845445
2006-10-29Fix when the IsDelayedCommit flag is set.Gabe Black
--HG-- extra : convert_revision : ab6cd69f82b2013d66a91beaa3e39d8f417a9251
2006-10-29Bring casa and casxa up to dateGabe Black
src/arch/sparc/isa/decoder.isa: Fix up the casa and casxa instructions. src/arch/sparc/isa/formats/formats.isa: This is handled in loadstore.isa now src/arch/sparc/isa/formats/mem/basicmem.isa: src/arch/sparc/isa/formats/mem/blockmem.isa: Renamed doSplitExecute to doDualSplitExecute. This differentiates between the version that does both a register and immediate version, and one that just does a register version. src/arch/sparc/isa/formats/mem/mem.isa: The cas format is handled in loadstore.isa as well now. src/arch/sparc/isa/formats/mem/util.isa: Reorganized things a bit to better support cas --HG-- extra : convert_revision : 12411e89e763287e52f9825bf7a417b263c1037f
2006-10-29Fixed ldstub to use the right format, and made the load/store operations use ↵Gabe Black
the integer microcode register. --HG-- extra : convert_revision : 7df5bd4bbe8a2607c7d2b4799826831d6a440926
2006-10-29Add an integer microcode register.Gabe Black
--HG-- extra : convert_revision : f23dbfdfe44e8e6cdd6948000669ad4f743b9fb4
2006-10-27Got rid of some outdated comments.Gabe Black
--HG-- extra : convert_revision : 30fa768c4a934cf5f9dc0ad84e0e421327ccbed3
2006-10-26Cleaned up the decoder slightly.Gabe Black
--HG-- extra : convert_revision : a7050aa8768c132f0161f00ba17ae02d71f0b829
2006-10-25Fixed the priv instruction format.Gabe Black
src/arch/sparc/isa/formats/priv.isa: Fix the priv format so that it uses isa_parser operands rather than accessing the registers directly in checkCode. Also, the expressions needed to be negated. src/arch/sparc/isa/operands.isa: Added an Hpstate operand, and adjusted the numbering. --HG-- extra : convert_revision : 4a70862df061aa9e1b9eab125c4c2fc839ac3b5a
2006-10-25Implemented the saved and restored instructions, fixed up register window ↵Gabe Black
instructions so that the cwp is modified at the correct time (when handling the fault), and fixed the "done" instruction. --HG-- extra : convert_revision : 3c9144422f087af1d375782cce1c9b77ca7936c9
2006-10-25Fixed the bitfield FCN to include the right bits.Gabe Black
--HG-- extra : convert_revision : 040beb4dd982784773c3c3ad04cc48c2dc98b58c
2006-10-23Move around more SPARC memory code, and make block memory operations work ↵Gabe Black
with the timing cpu --HG-- extra : convert_revision : 37358504c4d05d78d08c19ba3d0c99d38c4babf5
2006-10-23Broke Load/Store instructions into microcode, and partially refactored ↵Gabe Black
memory operations in the SPARC ISA description. --HG-- rename : src/arch/sparc/isa/formats.isa => src/arch/sparc/isa/formats/formats.isa rename : src/arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem/basicmem.isa rename : src/arch/sparc/isa/formats/blockmem.isa => src/arch/sparc/isa/formats/mem/blockmem.isa rename : src/arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem/mem.isa extra : convert_revision : dbbb00f997a102871b084b209b9fa08c5e1853ee
2006-10-23Start making memory ops work with InitiateAcc and CompleteAcc, and some ↵Gabe Black
minor cleanups --HG-- extra : convert_revision : 178a8c5d0506c75ad7a7e8d691c8863235ed7e95
2006-10-23Change the default constructors to take ExtMachInsts rather than regular ↵Gabe Black
MachInsts --HG-- extra : convert_revision : 8fa34f82e0cbf5ce81775d572b182826c578581f
2006-10-18Zeroed out the actual LSB in addition to moving it's original value the MSB.Gabe Black
--HG-- extra : convert_revision : d29efe01781d72ee6e61818e7b93972262c0616b
2006-10-18Fixed a compiler error, disassembly output, and corrected the address ↵Gabe Black
calculation. --HG-- extra : convert_revision : d34b3c0443064addb6f454ac70fbaeda0678e329
2006-10-18Fixed up ldblockf_p, implemented stdfa properly, and got rid of some old code.Gabe Black
--HG-- extra : convert_revision : 263b4b835d6d1bc9049acdc1398286277bede97a
2006-10-16Corrected the "Authors" lineGabe Black
--HG-- extra : convert_revision : 0202e130b170dcc2f45403c58cf51ec8c2e4e094
2006-10-16Fix up microcode support.Gabe Black
src/arch/sparc/isa/formats/blockmem.isa: Several small and medium bug fixes. src/cpu/simple/base.cc: Fixed a few compiler errors and made sure the next micro pc is set to 1 to prevent the first microop from executing twice. Also fixed a fetching bug. src/cpu/thread_state.cc: Made sure the microPC and nextMicroPC are initialized properly. --HG-- extra : convert_revision : a0fc8aa18d1ade916f17c557181a793c6108a8af
2006-10-16Changed how floating point register numbers are decoded to fit with the spec.Gabe Black
--HG-- extra : convert_revision : 155f48c84d06619c9c1c43375beb9d0a1c7495c9
2006-10-16Made sure the constructor for insts use ExtMachInst rather than MachInst, ↵Gabe Black
since otherwise the EXT_ASI field is lost. src/arch/sparc/isa/base.isa: src/arch/sparc/isa/formats/micro.isa: Switch MachInst to ExtMachInst so that the EXT_ASI field is available to the instructions. src/arch/sparc/utility.hh: Made sure EXT_ASI was set to the appropriate ASI value whether or not the asi register was used. --HG-- extra : convert_revision : cc4363dfe7da81969959cec9d5ad48528edeb8ce
2006-10-15Added an execute function to the macro op so it can be instantiated.Gabe Black
--HG-- extra : convert_revision : 89dd46f5bbac966e6eb4f6f747419fa1d344eb87
2006-10-15Fix how additional template parameters are handled. Non string parameters ↵Gabe Black
are not processed as code. src/arch/isa_parser.py: Changed the way the extra template parameters are specified. MIPS might need to be adjusted. src/arch/sparc/isa/decoder.isa: Changed how Frd_N was set up. src/arch/sparc/isa/formats/blockmem.isa: Fixed up handling of block memory operations src/arch/sparc/isa/formats/integerop.isa: src/arch/sparc/isa/formats/mem.isa: src/arch/sparc/isa/formats/priv.isa: Fix up extra template parameters. --HG-- extra : convert_revision : ebf850d192193521bb84ca36b577051f74338d23
2006-10-12Changed the sign extension function from mine to the provided one. Mine ↵Gabe Black
relied on implementation specific behavior, namely right shifting a signed value. --HG-- extra : convert_revision : 4f5ef44d012de87919ad681024fe2ed0213a412f
2006-10-12Some support for handling block loads and stores and ASIs properly.Gabe Black
src/arch/sparc/isa/bitfields.isa: Added a field to retrieve the asi from the ExtMachInst src/arch/sparc/isa/decoder.isa: Fixed up how the size of memory operations where handled, and use the new EXT_ASI bit field. src/arch/sparc/isa/formats.isa: add includes for the new formats. src/arch/sparc/isa/formats/basic.isa: Add a template for BasicDecodeWithMnemonic which is needed by the unimp format. src/arch/sparc/isa/formats/mem.isa: Change around the memory format to figure out the memory access width on its own. src/arch/sparc/isa/operands.isa: Added support for the operands of block loads/stores which are offset from Frd. src/arch/sparc/utility.hh: Encoded the ASI into the ExtMachInst --HG-- extra : convert_revision : 5c6026a07e3a919e738d27f78beb0faf6b060643
2006-10-12The beginnings of an instruction format to deal with block loads and stores. ↵Gabe Black
This takes advantage of microcode. --HG-- extra : convert_revision : ac912df76c781f40fc462f314451148c5cdfaf43
2006-10-12Some support for macro/micro instructions in SPARC.Gabe Black
--HG-- extra : convert_revision : 1f0687d58ab3a4823911a67d8d5c66b27cc211a5
2006-10-12Support for returning unimplemented instruction in the decoder, lifted from ↵Gabe Black
Alpha --HG-- extra : convert_revision : 7e26053696b23fbc0b8cd5827a5072dcf2526e2b
2006-09-03Make the ASI constants available to the decoder.Gabe Black
--HG-- extra : convert_revision : 65f2e02ce8f5e4f0c8727ebf16c927c7a6a4fe7f
2006-08-29Don't store if there's a fault.Gabe Black
--HG-- extra : convert_revision : fc852bee572b36daab7a34ee1820f856ccd71ca5
2006-08-29Cleaned up floating point by removing unnecessary conversions and by ↵Gabe Black
implementing faligndata more correctly. --HG-- extra : convert_revision : 44e778ce8f8d8606b6a50f3f12f0b87e1bf0ed66
2006-08-21Fix annulled unconditional branchesGabe Black
--HG-- extra : convert_revision : 698b0ce38c7a47306f97df2cc80cdae4a51b22c7
2006-08-21Two bugs found by my tracing tool.Gabe Black
1. alignaddr wrote it's address to a floating point register rather than a gpr. 2. sethi was sign extending it's immediate value. --HG-- extra : convert_revision : 9aa30a6485bc4cba916367973b986d439b7c7588
2006-08-17Changes to build m5.fastSteve Reinhardt
--HG-- extra : convert_revision : 2ec600b8e72e40e8b96e3b1dbe0334aa05e0f30b
2006-08-15Tweaks to Ali's changesGabe Black
--HG-- extra : convert_revision : ca2a81dd38012ae780f88cfd6be60f21fb43bb81
2006-08-15fixes for gcc 4.1Ali Saidi
Nate needs to fix sinic builder stuff Gabe needs to verify my fixes to decoder.isa OPT/DEBUG compiles for ALPHA_FS, ALPHA_SE, MIPS_SE, SPARC_SE with this changeset README: Fix the swig version in the readme src/SConscript: remove sinic until nate fixes the builder crap for it src/arch/alpha/system.hh: src/arch/mips/isa/includes.isa: src/arch/sparc/isa/decoder.isa: src/base/stats/visit.cc: src/base/timebuf.hh: src/dev/ide_disk.cc: src/dev/sinic.cc: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr_queue.cc: src/mem/packet.hh: src/mem/request.hh: src/sim/builder.hh: src/sim/system.hh: fixes for gcc 4.1 --HG-- extra : convert_revision : 3775427c0047b282574d4831dd602c96cac3ba17
2006-08-11Adjusted the decoder a little.Gabe Black
--HG-- extra : convert_revision : 5bdbe00342837ae4caacb3ad86c7becca36ba6ce
2006-07-26Added alot of fp instructions, and some impdep instructions.Gabe Black
--HG-- extra : convert_revision : cc703919b59e674044ae370a65dc03deece6d69e
2006-07-26Now ignore sigactionGabe Black
src/arch/sparc/isa/operands.isa: Added the GSR register as a control register --HG-- extra : convert_revision : 11ff4016d5c72468dd2daeba3a6105d4e84220ce
2006-07-22Fixed subtract with carry, and started some work with floating point.Gabe Black
src/arch/sparc/isa/decoder.isa: fixed subc, subccc, added decoding for impdep1 to fit with ua2005, and started work on floating point. src/arch/sparc/isa/operands.isa: Added in floating point operands, and changed the numbering of operands. src/arch/sparc/regfile.hh: Fixed some memory errors related to floating point. --HG-- extra : convert_revision : fa0aef2021a5cf99f175fceeb533fe63eb5f805c
2006-07-20Fixed a glitch in the disassembly output.Gabe Black
--HG-- extra : convert_revision : 833aa358b12ac987e0ab467708425c17e5a8fdb7
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