gem5 - gem5

Age	Commit message (Expand)	Author
2006-12-14	flesh out twinx asis	Ali Saidi
2006-12-12	Fix bugs in tlbmap (and thus rangemap since the code is nearly identical)	Ali Saidi
2006-12-08	Merge zizzer:/bk/sparcfs	Lisa Hsu
2006-12-08	mostly implemented SOFTINT relevant interrupt stuff.	Lisa Hsu
2006-12-07	get legion/m5 to first tlb miss fault	Ali Saidi
2006-12-06	Handle access to ASI_QUEUE	Ali Saidi
2006-12-06	Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts	Ali Saidi
2006-12-04	forgot to commit miscreg file	Ali Saidi
2006-12-04	More changes to get SPARC fs closer. Now at 1.2M cycles before difference	Ali Saidi
2006-11-29	Merge zizzer:/bk/sparcfs	Gabe Black
2006-11-24	Rename this function.	Gabe Black
2006-11-23	first cut at a sparc tlb	Ali Saidi
2006-11-22	Moved some constants from isa_traits.hh to the reg file headers.	Gabe Black
2006-11-20	Make sure only real bits of pstate can be set.	Gabe Black
2006-11-16	Fixes for SPARC_FS	Gabe Black
2006-11-14	Set hpstate to be what I'm assuming Legion is.	Gabe Black
2006-11-10	The reset function of the MiscRegFile really resets it now. This function is ...	Gabe Black
2006-11-10	Fix up instructions to read and write control registers, and got rid of the c...	Gabe Black
2006-11-03	Make things compile in SE again.	Gabe Black
2006-11-03	Move around misc reg code	Gabe Black
2006-11-01	Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register ...	Gabe Black
2006-10-27	Clean up MiscRegFile	Gabe Black
2006-10-26	Reorganized the MiscRegFile	Gabe Black
2006-10-26	Change the default function from setMiscRegWithEffect to setMiscReg	Gabe Black
2006-08-11	Pushed most of constants.hh back into isa_traits.hh and regfile.hh and create...	Gabe Black