gem5 - gem5

Age	Commit message (Expand)	Author
2007-03-07	MiscReg->MiscRegNoEffect, MiscRegWithEffect->MiscReg	Ali Saidi
2007-03-03	Fix some issues with 32 bit processes.	Gabe Black
2007-02-28	Make trap instructions always generate TrapInstruction Fault objects which ca...	Gabe Black
2006-12-20	Make sure the "stack_min" variable is page aligned.	Gabe Black
2006-12-05	Move the SyscallReturn class into sim/syscallreturn.hh. Also move some miscre...	Gabe Black
2006-11-24	Initial changes to get O3 working with SPARC	Gabe Black
2006-11-16	Implement current working directory for LiveProcesses	Nathan Binkert
2006-11-10	Set the ASI register to be something explicitly so that simulation is determi...	Gabe Black
2006-10-25	Implemented the SPARC fill and spill handlers.	Gabe Black
2006-09-17	Finished changing how stat structures are translated, fixed the handling of v...	Gabe Black
2006-09-03	Make the auxiliary vectors use the uid, euid, gid and egid parameters from th...	Gabe Black
2006-08-21	Got rid of the aux_data array since it shouldn't have existed.	Gabe Black
2006-08-17	Changes to build m5.fast	Steve Reinhardt
2006-08-11	Added code to support setting up all of the auxillieary vectors configured by...	Gabe Black
2006-06-11	Move LiveProcess::create() from arch-specific files	Steve Reinhardt
2006-06-06	Change ExecContext to ThreadContext. This is being renamed to differentiate ...	Kevin Lim
2006-05-31	Updated Authors from bk prs info	Ali Saidi
2006-05-26	Implement PR/HPR/ASR for full system	Ali Saidi
2006-05-22	New directory structure:	Steve Reinhardt