gem5 - gem5

Age	Commit message (Collapse)	Author
2007-01-30	Make SPARC checkpointing work	Ali Saidi
	src/arch/sparc/floatregfile.cc: Fix serialization for fpreg src/arch/sparc/intregfile.cc: fix serialization for intreg src/arch/sparc/miscregfile.cc: fix serialization from miscreg src/arch/sparc/pagetable.cc: fix serialization for page table src/arch/sparc/regfile.cc: need to serialize nnpc src/arch/sparc/tlb.cc: write serialization code for tlb src/cpu/base.cc: provide a way to find the thread number a context is serialize the instruction counter src/cpu/base.hh: provide a way to find the thread number a context is and given a thread number find a context pointer src/cpu/cpuevent.hh: provide method to get thread context from a cpu event for serialization src/dev/sparc/t1000.cc: src/dev/sparc/t1000.hh: nothing to serialize in t1000 src/sim/serialize.cc: src/sim/serialize.hh: Make findObj() work (it hasn't since we did the python conversion stuff) --HG-- extra : convert_revision : a95bc4e3c3354304171efbe3797556fdb146bea2
2007-01-26	Fixed the number of integer registers. There are MaxGL+1 sets of globals, ↵	Gabe Black
	not just MaxGL. --HG-- extra : convert_revision : 6fd090f112611db1e72a1f129dff03687d52930a
2007-01-22	Merge zizzer.eecs.umich.edu:/bk/newmem	Gabe Black
	into ewok.(none):/home/gblack/m5/newmemo3 src/sim/byteswap.hh: Hand Merge --HG-- extra : convert_revision : 640d33ad0c416934e8a5107768e7f1dce6709ca8
2007-01-20	fix InterruptLevel code to return the correct level	Ali Saidi
	(the bit positition that is set in softint) --HG-- extra : convert_revision : ba0e1f4ec1f74aac64c3f9bb7eb1b771e17b013a
2006-12-16	Merge zizzer:/bk/newmem	Gabe Black
	into zower.eecs.umich.edu:/eecshome/m5/newmem src/arch/isa_parser.py: src/arch/sparc/isa/formats/mem/basicmem.isa: src/arch/sparc/isa/formats/mem/blockmem.isa: src/arch/sparc/isa/formats/mem/util.isa: src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: src/cpu/o3/iew_impl.hh: Hand Merge --HG-- extra : convert_revision : ae1b25cde85ab8ec275a09d554acd372887d4d47
2006-12-06	Handle access to ASI_QUEUE	Ali Saidi
	Add function for interrupt ASIs add all the new MISCREGs to the copyMiscRegs() file src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: Add function for interrupt ASIs src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: Add QUEUE asi/misc registers src/arch/sparc/regfile.cc: add all the new MISCREGs to the copyMiscRegs() file src/arch/sparc/tlb.cc: Handle access to ASI_QUEUE --HG-- extra : convert_revision : 7a14450485816e6ee3bc8c80b462a13e1edf0ba0
2006-12-06	Some changes for misc regs which were changed into unofficial integer ↵	Gabe Black
	registers, and moved the flattenIndex function into the register file. --HG-- extra : convert_revision : 6b797c793a6c12c61a23f0f78a1ea1c88609553e
2006-11-24	Initial changes to get O3 working with SPARC	Gabe Black
	src/arch/sparc/process.cc: MachineBytes doesn't exist any more. src/arch/sparc/regfile.cc: Add in the miscRegFile for good measure. src/cpu/o3/isa_specific.hh: Add in a section for SPARC src/cpu/o3/sparc/cpu.cc: src/cpu/o3/sparc/cpu.hh: src/cpu/o3/sparc/cpu_builder.cc: src/cpu/o3/sparc/cpu_impl.hh: src/cpu/o3/sparc/dyn_inst.cc: src/cpu/o3/sparc/dyn_inst.hh: src/cpu/o3/sparc/dyn_inst_impl.hh: src/cpu/o3/sparc/impl.hh: src/cpu/o3/sparc/params.hh: src/cpu/o3/sparc/thread_context.cc: src/cpu/o3/sparc/thread_context.hh: Sparc version of this file. --HG-- extra : convert_revision : 34bb5218f802d0a1328132a518cdd769fb59b6a4
2006-11-01	Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register ↵	Gabe Black
	file functions to not take faults --HG-- extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
2006-10-27	Made the regfile compatible with the new definitions in MiscRegFile	Gabe Black
	--HG-- extra : convert_revision : d63ea6fb1e549e737204ee6653c06f89ec5e43ef
2006-08-11	Pushed most of constants.hh back into isa_traits.hh and regfile.hh and ↵	Gabe Black
	created a seperate file for the syscallreturn class. --HG-- extra : convert_revision : 9507ea1c09fda959f00aec9ec8ffb887ec8dd0f9