index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
arch
/
sparc
/
regfile.cc
Age
Commit message (
Expand
)
Author
2007-03-07
*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
Ali Saidi
2007-03-03
Implement Niagara I/O interface and rework interrupts
Ali Saidi
2007-01-30
Make SPARC checkpointing work
Ali Saidi
2007-01-26
Fixed the number of integer registers. There are MaxGL+1 sets of globals, not...
Gabe Black
2007-01-22
Merge zizzer.eecs.umich.edu:/bk/newmem
Gabe Black
2007-01-20
fix InterruptLevel code to return the correct level
Ali Saidi
2006-12-16
Merge zizzer:/bk/newmem
Gabe Black
2006-12-06
Handle access to ASI_QUEUE
Ali Saidi
2006-12-06
Some changes for misc regs which were changed into unofficial integer registe...
Gabe Black
2006-11-24
Initial changes to get O3 working with SPARC
Gabe Black
2006-11-01
Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register ...
Gabe Black
2006-10-27
Made the regfile compatible with the new definitions in MiscRegFile
Gabe Black
2006-08-11
Pushed most of constants.hh back into isa_traits.hh and regfile.hh and create...
Gabe Black