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path: root/src/arch/sparc/regfile.cc
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2007-01-20fix InterruptLevel code to return the correct levelAli Saidi
(the bit positition that is set in softint) --HG-- extra : convert_revision : ba0e1f4ec1f74aac64c3f9bb7eb1b771e17b013a
2006-12-06Handle access to ASI_QUEUEAli Saidi
Add function for interrupt ASIs add all the new MISCREGs to the copyMiscRegs() file src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: Add function for interrupt ASIs src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: Add QUEUE asi/misc registers src/arch/sparc/regfile.cc: add all the new MISCREGs to the copyMiscRegs() file src/arch/sparc/tlb.cc: Handle access to ASI_QUEUE --HG-- extra : convert_revision : 7a14450485816e6ee3bc8c80b462a13e1edf0ba0
2006-11-24Initial changes to get O3 working with SPARCGabe Black
src/arch/sparc/process.cc: MachineBytes doesn't exist any more. src/arch/sparc/regfile.cc: Add in the miscRegFile for good measure. src/cpu/o3/isa_specific.hh: Add in a section for SPARC src/cpu/o3/sparc/cpu.cc: src/cpu/o3/sparc/cpu.hh: src/cpu/o3/sparc/cpu_builder.cc: src/cpu/o3/sparc/cpu_impl.hh: src/cpu/o3/sparc/dyn_inst.cc: src/cpu/o3/sparc/dyn_inst.hh: src/cpu/o3/sparc/dyn_inst_impl.hh: src/cpu/o3/sparc/impl.hh: src/cpu/o3/sparc/params.hh: src/cpu/o3/sparc/thread_context.cc: src/cpu/o3/sparc/thread_context.hh: Sparc version of this file. --HG-- extra : convert_revision : 34bb5218f802d0a1328132a518cdd769fb59b6a4
2006-11-01Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register ↵Gabe Black
file functions to not take faults --HG-- extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
2006-10-27Made the regfile compatible with the new definitions in MiscRegFileGabe Black
--HG-- extra : convert_revision : d63ea6fb1e549e737204ee6653c06f89ec5e43ef
2006-08-11Pushed most of constants.hh back into isa_traits.hh and regfile.hh and ↵Gabe Black
created a seperate file for the syscallreturn class. --HG-- extra : convert_revision : 9507ea1c09fda959f00aec9ec8ffb887ec8dd0f9