gem5 - gem5

Age	Commit message (Collapse)	Author
2015-07-28	revert 5af8f40d8f2c	Nilay Vaish

2015-07-26	cpu: implements vector registers	Nilay Vaish
	This adds a vector register type. The type is defined as a std::array of a fixed number of uint64_ts. The isa_parser.py has been modified to parse vector register operands and generate the required code. Different cpus have vector register files now.
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
	Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
2013-10-15	cpu: rename _DepTag constants to _Reg_Base	Steve Reinhardt
	Make these names more meaningful. Specifically, made these substitutions: s/FP_Base_DepTag/FP_Reg_Base/g; s/Ctrl_Base_DepTag/Misc_Reg_Base/g; s/Max_DepTag/Max_Reg_Index/g;
2013-10-15	isa: clean up register constants	Steve Reinhardt
	Clean up and add some consistency to the *_Base_DepTag constants as well as some related register constants: - Get rid of NumMiscArchRegs, TotalArchRegs, and TotalDataRegs since they're never used and not always defined - Set FP_Base_DepTag = NumIntRegs when possible (i.e., every case except x86) - Set Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs (this was true before, but wasn't always expressed that way) - Drastically reduce the number of arbitrary constants appearing in these calculations
2012-06-05	O3: Clean up the O3 structures and try to pack them a bit better.	Ali Saidi
	DynInst is extremely large the hope is that this re-organization will put the most used members close to each other.
2012-04-23	ISA: Put parser generated files in a "generated" directory.	Gabe Black
	This is to avoid collision with non-generated files.
2011-06-09	sparc: compilation fixes for inorder	Korey Sewell
	Add a few constants and functions that the InOrder model wants for SPARC. * * * sparc: add eaComp function InOrder separates the address generation from the actual access so give Sparc that functionality * * * sparc: add control flags for branches branch predictors and other cpu model functions need to know specific information about branches, so add the necessary flags here
2010-11-11	SPARC: Clean up some historical style issues.	Gabe Black

2010-08-25	ARM: Fixed register flattening logic (FP_Base_DepTag was set too low)	Min Kyu Jeong
	When decoding a srs instruction, invalid mode encoding returns invalid instruction. This can happen when garbage instructions are fetched from mispredicted path
2009-07-08	Registers: Add a registers.hh file as an ISA switched header.	Gabe Black
	This file is for register indices, Num* constants, and register types. copyRegs and copyMiscRegs were moved to utility.hh and utility.cc. --HG-- rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh