gem5 - gem5

Age	Commit message (Expand)	Author
2018-11-05	sparc: Switch the FloatReg and FloatRegBits types to be 64 bit.	Gabe Black
2018-10-17	arch: Get rid of the unused type AnyReg.	Gabe Black
2017-07-05	cpu: Added interface for vector reg file	Rekai Gonzalez-Alberquilla
2017-07-05	arch, cpu: Architectural Register structural indexing	Nathanael Premillieu
2015-07-28	revert 5af8f40d8f2c	Nilay Vaish
2015-07-26	cpu: implements vector registers	Nilay Vaish
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
2013-10-15	cpu: rename _DepTag constants to _Reg_Base	Steve Reinhardt
2013-10-15	isa: clean up register constants	Steve Reinhardt
2012-06-05	O3: Clean up the O3 structures and try to pack them a bit better.	Ali Saidi
2012-04-23	ISA: Put parser generated files in a "generated" directory.	Gabe Black
2011-06-09	sparc: compilation fixes for inorder	Korey Sewell
2010-11-11	SPARC: Clean up some historical style issues.	Gabe Black
2010-08-25	ARM: Fixed register flattening logic (FP_Base_DepTag was set too low)	Min Kyu Jeong
2009-07-08	Registers: Add a registers.hh file as an ISA switched header.	Gabe Black