gem5 - gem5

Age	Commit message (Expand)	Author
2017-12-22	arch,cpu: "virtualize" the TLB interface.	Gabe Black
2016-11-09	style: [patch 1/22] use /r/3648/ to reorganize includes	Brandon Potter
2015-09-30	isa,cpu: Add support for FS SMT Interrupts	Mitch Hayenga
2015-07-07	sim: Refactor the serialization base class	Andreas Sandberg
2015-05-05	mem, cpu: Add a separate flag for strictly ordered memory	Andreas Sandberg
2014-10-16	arch: Use shared_ptr for all Faults	Andreas Hansson
2014-05-31	style: eliminate equality tests with true and false	Steve Reinhardt
2013-10-15	mem: Rename the ASI_BITS flag field in Request	Andreas Sandberg
2013-06-03	arch: Create a method to finalize physical addresses	Andreas Sandberg
2013-01-07	arch: Add support for invalidating TLBs when draining	Andreas Sandberg
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-03-09	CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPU	Geoffrey Blake
2011-10-13	SPARC: Remove the last checks of FULL_SYSTEM.	Gabe Black
2011-10-10	SPARC: Turn on handleIprRead and handleIprWrite in SE in SPARC.	Gabe Black
2011-06-19	sparc: init. cache state in TLB	Korey Sewell
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-15	includes: sort all includes	Nathan Binkert
2011-03-01	Spelling: Fix the a spelling error by changing mmaped to mmapped.	Gabe Black
2011-01-03	Make commenting on close namespace brackets consistent.	Steve Reinhardt
2010-11-11	SPARC: Clean up some historical style issues.	Gabe Black
2010-09-13	Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.	Gabe Black
2010-08-13	CPU: Tidy up endianness handling for mmapped "IPR"s.	Gabe Black
2009-08-01	Clean up some inconsistencies with Request flags.	Steve Reinhardt
2009-07-09	SPARC: Fold the MiscRegFile all the way into the ISA object.	Gabe Black
2009-04-08	tlb: More fixing of unified TLB	Nathan Binkert
2009-04-08	tlb: Don't separate the TLB classes into an instruction TLB and a data TLB	Gabe Black
2009-02-25	CPU: Implement translateTiming which defers to translateAtomic, and convert t...	Gabe Black
2009-02-25	ISA: Replace the translate functions in the TLBs with translateAtomic.	Gabe Black
2009-01-30	Errors: Use the correct panic/warn/fatal/info message in some places.	Ali Saidi
2008-11-10	mem: update stuff for changes to Packet and Request	Nathan Binkert
2008-10-21	style: Use the correct m5 style for things relating to interrupts.	Nathan Binkert
2008-10-12	CPU: Eliminate the get_vec function.	Gabe Black
2008-09-27	gcc: Add extra parens to quell warnings.	Nathan Binkert
2008-09-23	sparc: Fix style, create a helper function for translation.	Nathan Binkert
2008-02-26	TLB: Make a TLB base class and put a virtual demapPage function in it.	Gabe Black
2008-01-01	SPARC: Fix a bug where the TLB would match against the wrong entries.	Gabe Black
2007-11-30	SPARC: Fixes for invalidateAll and demapAll in the SPARC TLBs.	Gabe Black
2007-11-19	Serialization: Serialize SPARC PTEs last so their nameOut() calls don't inter...	Ali Saidi
2007-09-28	Rename cycles() function to ticks()	Ali Saidi
2007-08-30	params: Deprecate old-style constructors; update most SimObject constructors.	Miles Kaufmann
2007-08-26	Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.	Gabe Black
2007-08-26	SPARC: Make sure unaligned access are caught on cached translations as well.	Gabe Black
2007-08-13	SPARC: Move tlb state into the tlb.	Gabe Black
2007-08-13	SPARC: Make the spill and fill handlers use the correct ASI, and let No_Fault...	Gabe Black
2007-07-26	Merge python and x86 changes with cache branch	Nathan Binkert
2007-07-23	Major changes to how SimObjects are created and initialized. Almost all	Nathan Binkert
2007-06-30	Get rid of Packet result field. Error responses are	Steve Reinhardt
2007-03-08	Panic if any CMT registers are accessed	Ali Saidi
2007-03-07	MiscReg->MiscRegNoEffect, MiscRegWithEffect->MiscReg	Ali Saidi
2007-03-03	Implement Niagara I/O interface and rework interrupts	Ali Saidi