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ASI_BITS in the Request object were originally used to store a memory
request's ASI on SPARC. This is not the case any more since other ISAs
use the ASI bits to store architecture-dependent information. This
changeset renames the ASI_BITS to ARCH_BITS which better describes
their use. Additionally, the getAsi() accessor is renamed to
getArchFlags().
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in the TLB
Some architectures (currently only x86) require some fixing-up of
physical addresses after a normal address translation. This is usually
to remap devices such as the APIC, but could be used for other memory
mapped devices as well. When running the CPU in a using hardware
virtualization, we still need to do these address fix-ups before
inserting the request into the memory system. This patch moves this
patch allows that code to be used by such CPUs without doing full
address translations.
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This patch adds support for the memInvalidate() drain method. TLB
flushing is requested by calling the virtual flushAll() method on the
TLB.
Note: This patch renames invalidateAll() to flushAll() on x86 and
SPARC to make the interface consistent across all supported
architectures.
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This patch addresses the comments and feedback on the preceding patch
that reworks the clocks and now more clearly shows where cycles
(relative cycle counts) are used to express time.
Instead of bumping the existing patch I chose to make this a separate
patch, merely to try and focus the discussion around a smaller set of
changes. The two patches will be pushed together though.
This changes done as part of this patch are mostly following directly
from the introduction of the wrapper class, and change enough code to
make things compile and run again. There are definitely more places
where int/uint/Tick is still used to represent cycles, and it will
take some time to chase them all down. Similarly, a lot of parameters
should be changed from Param.Tick and Param.Unsigned to
Param.Cycles.
In addition, the use of curTick is questionable as there should not be
an absolute cycle. Potential solutions can be built on top of this
patch. There is a similar situation in the o3 CPU where
lastRunningCycle is currently counting in Cycles, and is still an
absolute time. More discussion to be had in other words.
An additional change that would be appropriate in the future is to
perform a similar wrapping of Tick and probably also introduce a
Ticks class along with suitable operators for all these classes.
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Making the CheckerCPU a runtime time option requires the code to be compatible
with ISAs other than ARM. This patch adds the appropriate function
stubs to allow compilation.
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valgrind complains and its a potential source of instability, so go ahead
and set it to 0 to start
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At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
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There may not be a formally correct spelling for the past tense of mmap, but
mmapped is the spelling Google doesn't try to autocorrect. This makes sense
because it mirrors the past tense of map->mapped and not the past tense of
cape->caped.
--HG--
rename : src/arch/alpha/mmaped_ipr.hh => src/arch/alpha/mmapped_ipr.hh
rename : src/arch/arm/mmaped_ipr.hh => src/arch/arm/mmapped_ipr.hh
rename : src/arch/mips/mmaped_ipr.hh => src/arch/mips/mmapped_ipr.hh
rename : src/arch/power/mmaped_ipr.hh => src/arch/power/mmapped_ipr.hh
rename : src/arch/sparc/mmaped_ipr.hh => src/arch/sparc/mmapped_ipr.hh
rename : src/arch/x86/mmaped_ipr.hh => src/arch/x86/mmapped_ipr.hh
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Ran all the source files through 'perl -pi' with this script:
s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|;
s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|;
s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;
Also did a little manual editing on some of the arch/*/isa_traits.hh files
and src/SConscript.
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Also move the "Fault" reference counted pointer type into a separate file,
sim/fault.hh. It would be better to name this less similarly to sim/faults.hh
to reduce confusion, but fault.hh matches the name of the type. We could change
Fault to FaultPtr to match other pointer types, and then changing the name of
the file would make more sense.
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the timing simple CPU to use it.
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Even though we're not incorrect about operator precedence, let's add
some parens in some particularly confusing places to placate GCC 4.3
so that we don't have to turn the warning off. Agreed that this is a
bit of a pain for those users who get the order of operations correct,
but it is likely to prevent bugs in certain cases.
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The translate function simplifies code and removes some compiler
warnings in gcc 3.4
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--HG--
extra : convert_revision : cc0e62a5a337fd5bf332ad33bed61c0d505a936f
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--HG--
extra : convert_revision : 631b3b6a1416121b54bd9717ca1cdccdd5b8a1eb
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--HG--
extra : convert_revision : 8de6c60b0e3e725eac11047a9d9888097dd359ff
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interfere with other serialization in the TLB.
--HG--
extra : convert_revision : 8a8478a200cd3c65b2ac98944d1278454811d38f
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--HG--
extra : convert_revision : 790eddb793d4f5ba35813d001037bd8601bd76a5
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SimObjects not yet updated:
- Process and subclasses
- BaseCPU and subclasses
The SimObject(const std::string &name) constructor was removed. Subclasses
that still rely on that behavior must call the parent initializer as
: SimObject(makeParams(name))
--HG--
extra : convert_revision : d6faddde76e7c3361ebdbd0a7b372a40941c12ed
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--HG--
extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
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--HG--
extra : convert_revision : 5c1f3f585817a19a771164f809dfc2fdc1ab3fb2
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Each "strand" may need to have a private copy of this state, but I couldn't
find anywhere in the spec that said that after looking briefly.
This prevents writes to the thread context in o3 which was causing the
pipeline to be flushed and stopping any forward progress. The other ASI
accessible state will probably need to be accessed differently if/when we get
O3 full system up and running.
--HG--
extra : convert_revision : fa7fba812d7f76564ef4a23818e60f536710d557
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No_Fault ASI accesses work.
--HG--
extra : convert_revision : 3321bb91da02c1bec27fa34d0ba945cc976b6491
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--HG--
extra : convert_revision : e06a950964286604274fba81dcca362d75847233
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creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.
--HG--
extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
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now encoded in cmd field.
--HG--
extra : convert_revision : d67819b7e3ee4b9a5bf08541104de0a89485e90b
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src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
add CMT ASI registers
src/arch/sparc/tlb.cc:
Panic if any of the CMT registers are being accessed
--HG--
extra : convert_revision : b9a94281e2074a576ac21d042b756950d509e758
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--HG--
extra : convert_revision : f799b65f1b2a6bf43605e6870b0f39b473dc492b
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configs/common/FSConfig.py:
Use binaries we've compiled instead of the ones that come with Legion
src/arch/alpha/interrupts.hh:
get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number
src/arch/sparc/asi.cc:
Add AsiIsInterrupt() to AsiIsMmu()
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
Add InterruptVector type
src/arch/sparc/interrupts.hh:
rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared
src/arch/sparc/isa_traits.hh:
Add the "interrupt" trap types to isa traits
src/arch/sparc/miscregfile.cc:
add names for all the misc registers and possible post an interrupt when TL is changed.
src/arch/sparc/miscregfile.hh:
Add a helper function to post an interrupt when pil < some set softint
src/arch/sparc/regfile.cc:
src/arch/sparc/regfile.hh:
InterruptLevel shouldn't really live here, moved to interrupt.hh
src/arch/sparc/tlb.cc:
Add interrupt ASIs to TLB
src/arch/sparc/ua2005.cc:
Add checkSoftInt to check if a softint needs to be posted
Check that a tickCompare isn't scheduled before scheduling one
Post and clear interrupts on queue writes and what not
src/base/bitfield.hh:
Add an helper function to return the msb that is set
src/cpu/base.cc:
src/cpu/base.hh:
get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending
src/cpu/intr_control.cc:
src/cpu/intr_control.hh:
src/dev/alpha/tsunami_cchip.cc:
src/python/m5/objects/IntrControl.py:
Make IntrControl have a system pointer rather than using a cpu pointer to get one
src/dev/sparc/SConscript:
add iob to SConsscrip
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out:
update config.ini/out for intrcntrl not having a cpu pointer anymore
--HG--
extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd
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into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision : 4105ebbeca59206bece27f229ee810d594fb4310
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util/m5/Makefile.alpha:
Clean up to make it a bit easier to muck with
util/m5/Makefile.alpha:
Make the makefile more reasonable
util/m5/Makefile.alpha:
Remove authors from copyright.
util/m5/Makefile.alpha:
Updated Authors from bk prs info
util/m5/Makefile.alpha:
bk cp Makefile Makefile.alpha
src/arch/sparc/tlb.cc:
Clean up the cache code a little bit and make sure the uncacbale bit is set when appropriate
src/arch/alpha/isa/decoder.isa:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
Rename AlphaPseudo -> PseudoInst since it's all generic
src/arch/sparc/isa/bitfields.isa:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/includes.isa:
src/arch/sparc/isa/operands.isa:
Add support for pseudo instructions in sparc
util/m5/Makefile.alpha:
util/m5/Makefile.sparc:
split off alpha make file and sparc make file for m5 app
util/m5/m5.c:
ivle and ivlb aren't used anymore
util/m5/m5op.h:
stdint seems like a more generic better fit here
util/m5/m5op_alpha.S:
move the op ids into their own header file since we can share them between sparc and alpha
--HG--
rename : util/m5/Makefile => util/m5/Makefile.sparc
rename : util/m5/m5op.S => util/m5/m5op_alpha.S
extra : convert_revision : 490ba2e8b8bc6e28bfc009cedec6b686b28e7834
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This basically involves moving the builder code outside of any
namespace. While we're at it, move a few braces outside of
a couple #if/#else/#endif blocks so it's easier to match up
the braces.
--HG--
extra : convert_revision : a7834532aadc63b0e0ff988dd5745049e02e6312
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src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
src/arch/sparc/arguments.hh:
move Copy* to vport since it's generic for all the ISAs
src/arch/sparc/isa_traits.hh:
the Solaris kernel sets up a virtual-> real mapping for all memory starting at SegKPMBase
src/arch/sparc/pagetable.hh:
add a class for getting bits out of the TteTag
src/arch/sparc/remote_gdb.cc:
add 32bit support kinda.... If its 32 bit
src/arch/sparc/remote_gdb.hh:
Add 32bit register offsets too.
src/arch/sparc/tlb.cc:
cleanup generation of tsb pointers
src/arch/sparc/tlb.hh:
add function to return tsb pointers for an address
make lookup public so vtophys can use it
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
write vtophys for sparc
src/base/bitfield.hh:
return a mask of bits first->last
src/mem/vport.cc:
src/mem/vport.hh:
move Copy* here since it's ISA generic
--HG--
extra : convert_revision : c42c331e396c0d51a2789029d8e232fe66995d0f
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src/arch/sparc/isa/decoder.isa:
fix rdgsr fault check
src/arch/sparc/tlb.cc:
block asis are now supported
--HG--
extra : convert_revision : cf55d648d2c5184fab03b6fe057d0e33c1dfc393
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src/SConscript:
strip doesn't take a src and dest in solaris
--HG--
extra : convert_revision : 57f95eda0e3232475a5b55753ace3f3f0fced8b3
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src/arch/sparc/floatregfile.cc:
Fix serialization for fpreg
src/arch/sparc/intregfile.cc:
fix serialization for intreg
src/arch/sparc/miscregfile.cc:
fix serialization from miscreg
src/arch/sparc/pagetable.cc:
fix serialization for page table
src/arch/sparc/regfile.cc:
need to serialize nnpc
src/arch/sparc/tlb.cc:
write serialization code for tlb
src/cpu/base.cc:
provide a way to find the thread number a context is
serialize the instruction counter
src/cpu/base.hh:
provide a way to find the thread number a context is
and given a thread number find a context pointer
src/cpu/cpuevent.hh:
provide method to get thread context from a cpu event for serialization
src/dev/sparc/t1000.cc:
src/dev/sparc/t1000.hh:
nothing to serialize in t1000
src/sim/serialize.cc:
src/sim/serialize.hh:
Make findObj() work (it hasn't since we did the python conversion stuff)
--HG--
extra : convert_revision : a95bc4e3c3354304171efbe3797556fdb146bea2
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