summaryrefslogtreecommitdiff
path: root/src/arch/sparc/tlb.cc
AgeCommit message (Expand)Author
2017-12-22arch,cpu: "virtualize" the TLB interface.Gabe Black
2016-11-09style: [patch 1/22] use /r/3648/ to reorganize includesBrandon Potter
2015-09-30isa,cpu: Add support for FS SMT InterruptsMitch Hayenga
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2015-05-05mem, cpu: Add a separate flag for strictly ordered memoryAndreas Sandberg
2014-10-16arch: Use shared_ptr for all FaultsAndreas Hansson
2014-05-31style: eliminate equality tests with true and falseSteve Reinhardt
2013-10-15mem: Rename the ASI_BITS flag field in RequestAndreas Sandberg
2013-06-03arch: Create a method to finalize physical addressesAndreas Sandberg
2013-01-07arch: Add support for invalidating TLBs when drainingAndreas Sandberg
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-03-09CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPUGeoffrey Blake
2011-10-13SPARC: Remove the last checks of FULL_SYSTEM.Gabe Black
2011-10-10SPARC: Turn on handleIprRead and handleIprWrite in SE in SPARC.Gabe Black
2011-06-19sparc: init. cache state in TLBKorey Sewell
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-04-15includes: sort all includesNathan Binkert
2011-03-01Spelling: Fix the a spelling error by changing mmaped to mmapped.Gabe Black
2011-01-03Make commenting on close namespace brackets consistent.Steve Reinhardt
2010-11-11SPARC: Clean up some historical style issues.Gabe Black
2010-09-13Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.Gabe Black
2010-08-13CPU: Tidy up endianness handling for mmapped "IPR"s.Gabe Black
2009-08-01Clean up some inconsistencies with Request flags.Steve Reinhardt
2009-07-09SPARC: Fold the MiscRegFile all the way into the ISA object.Gabe Black
2009-04-08tlb: More fixing of unified TLBNathan Binkert
2009-04-08tlb: Don't separate the TLB classes into an instruction TLB and a data TLBGabe Black
2009-02-25CPU: Implement translateTiming which defers to translateAtomic, and convert t...Gabe Black
2009-02-25ISA: Replace the translate functions in the TLBs with translateAtomic.Gabe Black
2009-01-30Errors: Use the correct panic/warn/fatal/info message in some places.Ali Saidi
2008-11-10mem: update stuff for changes to Packet and RequestNathan Binkert
2008-10-21style: Use the correct m5 style for things relating to interrupts.Nathan Binkert
2008-10-12CPU: Eliminate the get_vec function.Gabe Black
2008-09-27gcc: Add extra parens to quell warnings.Nathan Binkert
2008-09-23sparc: Fix style, create a helper function for translation.Nathan Binkert
2008-02-26TLB: Make a TLB base class and put a virtual demapPage function in it.Gabe Black
2008-01-01SPARC: Fix a bug where the TLB would match against the wrong entries.Gabe Black
2007-11-30SPARC: Fixes for invalidateAll and demapAll in the SPARC TLBs.Gabe Black
2007-11-19Serialization: Serialize SPARC PTEs last so their nameOut() calls don't inter...Ali Saidi
2007-09-28Rename cycles() function to ticks()Ali Saidi
2007-08-30params: Deprecate old-style constructors; update most SimObject constructors.Miles Kaufmann
2007-08-26Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.Gabe Black
2007-08-26SPARC: Make sure unaligned access are caught on cached translations as well.Gabe Black
2007-08-13SPARC: Move tlb state into the tlb.Gabe Black
2007-08-13SPARC: Make the spill and fill handlers use the correct ASI, and let No_Fault...Gabe Black
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt
2007-03-08Panic if any CMT registers are accessedAli Saidi
2007-03-07*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscRegAli Saidi
2007-03-03Implement Niagara I/O interface and rework interruptsAli Saidi