gem5 - gem5

Age	Commit message (Expand)	Author
2007-01-22	use writeTagAccess() function to unify writing of Tag access registers	Ali Saidi
2007-01-21	make sure that page bits of VA on tlb insert are 0	Ali Saidi
2007-01-20	atually set all 64 bits of the retun value to 0	Ali Saidi
2007-01-20	Rearange tlb code to remove some duplicate	Ali Saidi
2007-01-17	Allow ASI_LDTX_REAL	Ali Saidi
2007-01-17	do a linear search for matching tlb entries instead of using map because you ...	Ali Saidi
2007-01-17	Implement reading writing of sync fault status register and address register	Ali Saidi
2007-01-16	In the case of ASI_P or ASI_LDTX_P set primary and skip the other checks	Ali Saidi
2007-01-09	quiet/remove some warnings	Ali Saidi
2006-12-27	Bug fixes in the TLB	Ali Saidi
2006-12-19	fix twinx loads a little bit	Ali Saidi
2006-12-18	move the twinx loads to the correct opcode and add asis 0x24 and 0x27	Ali Saidi
2006-12-15	Optimized the TLB translations with some caching	Ali Saidi
2006-12-14	flesh out twinx asis	Ali Saidi
2006-12-12	Fix bugs in tlbmap (and thus rangemap since the code is nearly identical)	Ali Saidi
2006-12-09	Allocate the correct number of global registers	Ali Saidi
2006-12-07	get legion/m5 to first tlb miss fault	Ali Saidi
2006-12-06	Handle access to ASI_QUEUE	Ali Saidi
2006-12-06	Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts	Ali Saidi
2006-11-29	Add TLB Dprintfs	Ali Saidi
2006-11-29	Add support for mmapped iprs to atomic cpu	Ali Saidi
2006-11-23	first cut at a sparc tlb	Ali Saidi
2006-11-08	Stubs for SPARC's tlbs	Gabe Black