gem5 - gem5

Age	Commit message (Collapse)	Author
2009-07-08	Registers: Get rid of the float register width parameter.	Gabe Black

2009-05-17	includes: use base/types.hh not inttypes.h or stdint.h	Nathan Binkert

2008-10-12	Get rid of old RegContext code.	Gabe Black

2007-11-15	Add CoreSpecific type to all archs	Korey Sewell
	--HG-- extra : convert_revision : 659786bf6489ab6151e47fbf1f4c0a723262fce2
2007-08-27	SPARC: Fixes to get SPARC to compile again.	Gabe Black
	--HG-- extra : convert_revision : dab20c49fec9c2d385ca59b9ab627c2d3dddfe76
2007-08-26	Address translation: Make the page table more flexible.	Gabe Black
	The page table now stores actual page table entries. It is still a templated class here, but this will be corrected in the near future. --HG-- extra : convert_revision : 804dcc6320414c2b3ab76a74a15295bd24e1d13d
2007-04-14	Make register indexes larger so they can actually hold all the legal values. ↵	Gabe Black
	Oops! --HG-- extra : convert_revision : 7689b2e1f7468e4acb8be0f242f74002c79e7960
2007-02-12	rename store conditional stuff as extra data so it can be used for ↵	Ali Saidi
	conditional swaps as well Add support for a twin 64 bit int load Add Memory barrier and write barrier flags as appropriate Make atomic memory ops atomic src/arch/alpha/isa/mem.isa: src/arch/alpha/locked_mem.hh: src/cpu/base_dyn_inst.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_impl.hh: rename store conditional stuff as extra data so it can be used for conditional swaps as well src/arch/alpha/types.hh: src/arch/mips/types.hh: src/arch/sparc/types.hh: add a largest read data type for statically allocating read buffers in atomic simple cpu src/arch/isa_parser.py: Add support for a twin 64 bit int load src/arch/sparc/isa/decoder.isa: Make atomic memory ops atomic Add Memory barrier and write barrier flags as appropriate src/arch/sparc/isa/formats/mem/basicmem.isa: add post access code block and define a twinload format for twin loads src/arch/sparc/isa/formats/mem/blockmem.isa: remove old microcoded twin load coad src/arch/sparc/isa/formats/mem/mem.isa: swap.isa replaces the code in loadstore.isa src/arch/sparc/isa/formats/mem/util.isa: add a post access code block src/arch/sparc/isa/includes.isa: need bigint.hh for Twin64_t src/arch/sparc/isa/operands.isa: add a twin 64 int type src/cpu/simple/atomic.cc: src/cpu/simple/atomic.hh: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: add support for twinloads add support for swap and conditional swap instructions rename store conditional stuff as extra data so it can be used for conditional swaps as well src/mem/packet.cc: src/mem/packet.hh: Add support for atomic swap memory commands src/mem/packet_access.hh: Add endian conversion function for Twin64_t type src/mem/physical.cc: src/mem/physical.hh: src/mem/request.hh: Add support for atomic swap memory commands Rename sc code to extradata --HG-- extra : convert_revision : 69d908512fb34a4e28b29a6e58b807fb1a6b1656
2006-08-11	Pushed most of constants.hh back into isa_traits.hh and regfile.hh and ↵	Gabe Black
	created a seperate file for the syscallreturn class. --HG-- extra : convert_revision : 9507ea1c09fda959f00aec9ec8ffb887ec8dd0f9