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2018-03-27sparc: Add some missing M5_FALLTHROUGHs and breaks.Gabe Black
These fix what I believe are some bugs, and also some gcc warnings. Change-Id: I5fb2a1b2f0ef3643b25aaf0c29c096996ef98ec0 Reviewed-on: https://gem5-review.googlesource.com/9402 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2016-11-09style: [patch 1/22] use /r/3648/ to reorganize includesBrandon Potter
2015-09-30isa,cpu: Add support for FS SMT InterruptsMitch Hayenga
Adds per-thread interrupt controllers and thread/context logic so that interrupts properly get routed in SMT systems.
2015-09-15sparc: writing to tick_cmpr should not cause a panicPalle Lyckegaard
This register is writable according to UA2005 Tried to boot NetBSD which starts the kernel by writing to the tick_cmpr register. Without the patch gem5 crashes with a panic. With the patch NetBSD starts to boot normally (although sun4v support in NetBSD is not complete yet) Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
This patch addresses the comments and feedback on the preceding patch that reworks the clocks and now more clearly shows where cycles (relative cycle counts) are used to express time. Instead of bumping the existing patch I chose to make this a separate patch, merely to try and focus the discussion around a smaller set of changes. The two patches will be pushed together though. This changes done as part of this patch are mostly following directly from the introduction of the wrapper class, and change enough code to make things compile and run again. There are definitely more places where int/uint/Tick is still used to represent cycles, and it will take some time to chase them all down. Similarly, a lot of parameters should be changed from Param.Tick and Param.Unsigned to Param.Cycles. In addition, the use of curTick is questionable as there should not be an absolute cycle. Potential solutions can be built on top of this patch. There is a similar situation in the o3 CPU where lastRunningCycle is currently counting in Cycles, and is still an absolute time. More discussion to be had in other words. An additional change that would be appropriate in the future is to perform a similar wrapping of Tick and probably also introduce a Ticks class along with suitable operators for all these classes.
2012-02-11SPARC: Make PSTATE and HPSTATE a BitUnion.Gabe Black
This gets rid of cryptic bits of code with lots of bit manipulation, and makes some comments redundant.
2011-10-31SE/FS: Remove the last uses of FULL_SYSTEM from SPARC.Gabe Black
2011-10-09[mq]: sefssparcregfile.patchGabe Black
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values.
2010-11-11SPARC: Clean up some historical style issues.Gabe Black
2009-07-09SPARC: Fold the MiscRegFile all the way into the ISA object.Gabe Black
2009-04-15Get rid of the Unallocated thread context state.Steve Reinhardt
Basically merge it in with Halted. Also had to get rid of a few other functions that called ThreadContext::deallocate(), including: - InOrderCPU's setThreadRescheduleCondition. - ThreadContext::exit(). This function was there to avoid terminating simulation when one thread out of a multi-thread workload exits, but we need to find a better (non-cpu-centric) way.
2009-02-25ISA: Get rid of the get*RegName functions.Gabe Black
2008-11-05Fix a few more places where the context stuff wasn't changedNathan Binkert
2008-11-02Add in Context IDs to the simulator. From now on, cpuId is almost never used,Lisa Hsu
the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate.
2008-11-02make BaseCPU the provider of _cpuId, and cpuId() instead of being scatteredLisa Hsu
across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch.
2008-10-21style: Use the correct m5 style for things relating to interrupts.Nathan Binkert
2008-10-09eventq: convert all usage of events to use the new API.Nathan Binkert
For now, there is still a single global event queue, but this is necessary for making the steps towards a parallelized m5.
2008-08-11styleNathan Binkert
2007-09-28Rename cycles() function to ticks()Ali Saidi
--HG-- extra : convert_revision : 790eddb793d4f5ba35813d001037bd8601bd76a5
2007-03-13fix interrupting during a quisce on sparcAli Saidi
src/arch/sparc/ua2005.cc: fix interrupting when quisced. Since sticks correspond to instructions when not quisced we need to check if were suspended and interrupt at the guess time src/base/traceflags.py: add trace flag for Iob src/cpu/simple/base.cc: Use Quisce instead of IPI trace flag src/dev/sparc/iob.cc: add some Dprintfs --HG-- extra : convert_revision : 72e18fcc750ad1e4b2bb67b19b354eaffc6af6d5
2007-03-12move hver code to ua2005.ccAli Saidi
src/arch/sparc/miscregfile.cc: this code should be in readFSreg src/arch/sparc/ua2005.cc: move code froh miscregfile to ua2005.cc --HG-- extra : convert_revision : fa450b04ad73ab6f6e25d66fa0368054263f09f9
2007-03-09implement ipi stufff for SPARCAli Saidi
src/arch/alpha/utility.hh: src/arch/mips/utility.hh: src/arch/sparc/utility.hh: src/arch/x86/utility.hh: add hook for system to startup the cpu or not... in the case of FS sparc, only the first cpu would get spunup.. the rest sit in an idle state until they get an ipi src/arch/sparc/isa/decoder.isa: handle writable bits of strandstatus register in miscregfile src/arch/sparc/miscregfile.hh: some constants for the strand status register src/arch/sparc/ua2005.cc: properly implement the strand status register src/dev/sparc/iob.cc: implement ipi generation properly src/sim/system.cc: call into the ISA to start the CPU (or not) --HG-- extra : convert_revision : 0003b2032337d8a031a9fc044da726dbb2a9e36f
2007-03-07I missed a couple of WithEffects, this should do itAli Saidi
--HG-- extra : convert_revision : 19fce78a19b27b7ccb5e3653a64b46e6d5292915
2007-03-07*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscRegAli Saidi
--HG-- extra : convert_revision : f799b65f1b2a6bf43605e6870b0f39b473dc492b
2007-03-03Implement Niagara I/O interface and rework interruptsAli Saidi
configs/common/FSConfig.py: Use binaries we've compiled instead of the ones that come with Legion src/arch/alpha/interrupts.hh: get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number src/arch/sparc/asi.cc: Add AsiIsInterrupt() to AsiIsMmu() src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: Add InterruptVector type src/arch/sparc/interrupts.hh: rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared src/arch/sparc/isa_traits.hh: Add the "interrupt" trap types to isa traits src/arch/sparc/miscregfile.cc: add names for all the misc registers and possible post an interrupt when TL is changed. src/arch/sparc/miscregfile.hh: Add a helper function to post an interrupt when pil < some set softint src/arch/sparc/regfile.cc: src/arch/sparc/regfile.hh: InterruptLevel shouldn't really live here, moved to interrupt.hh src/arch/sparc/tlb.cc: Add interrupt ASIs to TLB src/arch/sparc/ua2005.cc: Add checkSoftInt to check if a softint needs to be posted Check that a tickCompare isn't scheduled before scheduling one Post and clear interrupts on queue writes and what not src/base/bitfield.hh: Add an helper function to return the msb that is set src/cpu/base.cc: src/cpu/base.hh: get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending src/cpu/intr_control.cc: src/cpu/intr_control.hh: src/dev/alpha/tsunami_cchip.cc: src/python/m5/objects/IntrControl.py: Make IntrControl have a system pointer rather than using a cpu pointer to get one src/dev/sparc/SConscript: add iob to SConsscrip tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out: update config.ini/out for intrcntrl not having a cpu pointer anymore --HG-- extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd
2007-01-26Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5 --HG-- extra : convert_revision : 1b854ec7caa33d3009383754206b643494c4c42d
2007-01-26eliminate cpu checkInterrupts bool, it is redundant and unnecessary.Lisa Hsu
--HG-- extra : convert_revision : 58e960e5019f944c7ec5606e4b8c93ce42330719
2007-01-22clean up fault code a little bitAli Saidi
simplify and make complete some asi checks implement all the twin asis and remove panic checks on their use soft int is supported, so we don't need to print writes to it src/arch/sparc/asi.cc: make AsiIsLittle() be all the little asis. Speed up AsiIsTwin() a bit src/arch/sparc/faults.cc: clean up the do*Fault code.... Make it work like legion, in particular pstate.priv is left alone, not set to 0 like the spec says src/arch/sparc/isa/decoder.isa: implement some more twin ASIs src/arch/sparc/tlb.cc: All the twin asis are implemented, no need to say their not supported anymore src/arch/sparc/ua2005.cc: softint is supported now, no more need to --HG-- extra : convert_revision : aef2a1b93719235edff830a17a8ec52f23ec9f8b
2007-01-19some hstick and hintp changes.Lisa Hsu
src/arch/sparc/interrupts.hh: condition hstick matches on HINTP src/arch/sparc/miscregfile.cc: implement HINTP src/arch/sparc/ua2005.cc: don't post interrupt unless it is enabled. --HG-- extra : convert_revision : f71d1c1d9fd1a898ddafd5a885c3a8d5c75e8ff0
2007-01-11Merge zed.eecs.umich.edu:/z/hsul/work/sparc/ali.m5Lisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 src/arch/sparc/ua2005.cc: hand merge between ali and me. --HG-- extra : convert_revision : 810d63fb484ab26fc30f8130ef32390ba149b267
2007-01-11ua2005.cc:Lisa Hsu
formatting/indentation for case statements src/arch/sparc/ua2005.cc: formatting/indentation for case statements --HG-- extra : convert_revision : aeb7d0274d8d22db3fa56aabbb8ab8f5371a32ff
2007-01-11ua2005.cc:Lisa Hsu
i SWEAR i committed this already, but apparently i didnt. ust start using HPSTATE::hpriv, etc. to access bitfields. src/arch/sparc/ua2005.cc: i SWEAR i committed this already, but apparently i didnt. ust start using HPSTATE::hpriv, etc. to access bitfields. --HG-- extra : convert_revision : e66fac9c63088c0fc1a62bd0fac92df305beadff
2007-01-09quiet/remove some warningsAli Saidi
fix implementation of cwp manipulation implement PS0 and PS1 IMMU asis src/arch/sparc/miscregfile.cc: get rid of some warnings fix implementation of setting cwp to saturate cwp since it appears the os sets it to a large value to see how many there actually are src/arch/sparc/tlb.cc: implement PS0 and PS1 IMMU access ASIs src/arch/sparc/ua2005.cc: make warning less verbose --HG-- extra : convert_revision : 442b65dfc41ebc32b2ef0e6b80da94eee3be9cd3
2007-01-08the way i understand it, interrupts in m5 is a little bloated. the usage of ↵Lisa Hsu
CPU->checkInterrupts bool is inconsistent, and i think should eventually be phased out. For now, I've just assumed that CPU->checkInterrupts() is the way to fast path a CPU if you have no interrupts by having a simple bitfield in each ISA to determine whether interrupts are pending. getInterrupts has been mostly filled in. src/arch/sparc/interrupts.hh: fill in how we do interrupts on sparc a little bit. 1) create a bitfield for interrupts, and check that in checkInterrupts() to fast path CPU. 2) fill in getInterrupts() a little bit. also, update the bitfield access to be HPSTATE::hpriv, etc. src/arch/sparc/ua2005.cc: 1) update formatting 2) change the way interrupts are done to use the new way to tickle the CPU. src/cpu/base.cc: src/cpu/base.hh: overload the post_interrupt function for SPARC interrupts - which are only denoted by a single int value. --HG-- extra : convert_revision : 9074a003eff37a40dcce78f56d20f6cbcc453eb5
2007-01-08fix softint and partially implement hstick interrupts need to figure out how ↵Ali Saidi
to do the acutal interrupting still src/arch/sparc/miscregfile.cc: fix softint and fprs in miscregfile --HG-- extra : convert_revision : cf98bd9c172e20f328f18e07dd05f63f37f14c87
2007-01-05set the softint appropriately on an timer compare interruptAli Saidi
there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly src/arch/sparc/faults.cc: there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly src/arch/sparc/faults.hh: correct protection defines src/arch/sparc/ua2005.cc: set the softint appropriately on an timer compare interrupt --HG-- extra : convert_revision : f41c10ec78db973b3f856c70b58a17f83b60bbe2
2007-01-04Fix stick compare to work correctly and set checkInterrupts to true at the ↵Ali Saidi
appropriate time turn warnings into dprintfs src/arch/sparc/miscregfile.cc: turn dprintfn into dprintfs --HG-- extra : convert_revision : cd313e9037c8f040d837de4c7ddbcf98534e60ad
2006-12-09fix lisa's hand mergeAli Saidi
--HG-- extra : convert_revision : d25604156ae0b2cf29d92fb960b8f5d77427985b
2006-12-08Merge zizzer:/bk/sparcfsLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 src/arch/sparc/ua2005.cc: hand merge --HG-- extra : convert_revision : 5157fa5d7053cb93f73241c63871eaae6f58b8a6
2006-12-08mostly implemented SOFTINT relevant interrupt stuff.Lisa Hsu
src/arch/sparc/interrupts.hh: add in thread_context.hh to get access to tc. get rid of stubs that don't make sense right now. implement checking and get softint interrupts src/arch/sparc/miscregfile.cc: softint should be OR-ed on a write. src/arch/sparc/miscregfile.hh: add some enums for state fields for easy access to bitmasks of HPSTATE and PSTATE regs. src/arch/sparc/ua2005.cc: implement writing SOFTINT, PSTATE, PIL, and HPSTATE properly, add helpful info to panic for bad reg write. --HG-- extra : convert_revision : d12d1147b508121075ee9be4599693554d4b9eae
2006-12-07get legion/m5 to first tlb miss faultAli Saidi
src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: add sparc error asi src/arch/sparc/faults.cc: put a panic in if TL == MaxTL src/arch/sparc/isa/decoder.isa: Hpstate needs to be updated on a done too src/arch/sparc/miscregfile.cc: warn istead of panicing of fprs/fsr accesses src/arch/sparc/tlb.cc: add sparc error register code that just does nothing fix a couple of other tlb bugs src/arch/sparc/ua2005.cc: fix implementation of HPSTATE write src/cpu/exetrace.cc: let exectrate mess up a couple of times before dying src/python/m5/objects/T1000.py: add l2 error status register fake devices --HG-- extra : convert_revision : ed5dfdfb28633bf36e5ae07d244f7510a02874ca
2006-12-04reogranize code to split off FS only misc regs with effect into their own ↵Ali Saidi
file (reducing the number of if FULL_SYSTEM defines and includes) Protect other pieces of code so that sparc compiles SE again src/arch/sparc/SConscript: Add ua2005.cc back into SConscript src/arch/sparc/miscregfile.hh: add functions that deal with priv registers so we don't have to have a bunch of if defs and other ugliness src/arch/sparc/mmaped_ipr.hh: wrap handleIpr* with if full_system so it compiles under se src/arch/sparc/ua2005.cc: reorganize edit fs only miscreg functions src/cpu/exetrace.cc: protect legion code so it doesn't try to compile under se --HG-- extra : convert_revision : 6b3c9f6f95b4da8544525f4f82e92861383ede76
2006-08-14Fix up doxygen.Steve Reinhardt
--HG-- rename : docs/footer.html => src/doxygen/footer.html rename : docs/stl.hh => src/doxygen/stl.hh extra : convert_revision : 2b2e5637930843c1be07deaa708fd4126213cda2
2006-06-06Change ExecContext to ThreadContext. This is being renamed to differentiate ↵Kevin Lim
between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar. src/arch/alpha/arguments.cc: src/arch/alpha/arguments.hh: src/arch/alpha/ev5.cc: src/arch/alpha/faults.cc: src/arch/alpha/faults.hh: src/arch/alpha/freebsd/system.cc: src/arch/alpha/freebsd/system.hh: src/arch/alpha/isa/branch.isa: src/arch/alpha/isa/decoder.isa: src/arch/alpha/isa/main.isa: src/arch/alpha/linux/process.cc: src/arch/alpha/linux/system.cc: src/arch/alpha/linux/system.hh: src/arch/alpha/linux/threadinfo.hh: src/arch/alpha/process.cc: src/arch/alpha/regfile.hh: src/arch/alpha/stacktrace.cc: src/arch/alpha/stacktrace.hh: src/arch/alpha/tlb.cc: src/arch/alpha/tlb.hh: src/arch/alpha/tru64/process.cc: src/arch/alpha/tru64/system.cc: src/arch/alpha/tru64/system.hh: src/arch/alpha/utility.hh: src/arch/alpha/vtophys.cc: src/arch/alpha/vtophys.hh: src/arch/mips/faults.cc: src/arch/mips/faults.hh: src/arch/mips/isa_traits.cc: src/arch/mips/isa_traits.hh: src/arch/mips/linux/process.cc: src/arch/mips/process.cc: src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/int_regfile.hh: src/arch/mips/regfile/misc_regfile.hh: src/arch/mips/regfile/regfile.hh: src/arch/mips/stacktrace.hh: src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: src/arch/sparc/isa_traits.hh: src/arch/sparc/linux/process.cc: src/arch/sparc/linux/process.hh: src/arch/sparc/process.cc: src/arch/sparc/regfile.hh: src/arch/sparc/solaris/process.cc: src/arch/sparc/stacktrace.hh: src/arch/sparc/ua2005.cc: src/arch/sparc/utility.hh: src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: src/base/remote_gdb.cc: src/base/remote_gdb.hh: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.cc: src/cpu/checker/cpu.hh: src/cpu/checker/exec_context.hh: src/cpu/cpu_exec_context.cc: src/cpu/cpu_exec_context.hh: src/cpu/cpuevent.cc: src/cpu/cpuevent.hh: src/cpu/exetrace.hh: src/cpu/intr_control.cc: src/cpu/memtest/memtest.hh: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/commit.hh: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/regfile.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/back_end.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/inorder_back_end.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_back_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/thread_state.hh: src/cpu/pc_event.cc: src/cpu/pc_event.hh: src/cpu/profile.cc: src/cpu/profile.hh: src/cpu/quiesce_event.cc: src/cpu/quiesce_event.hh: src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: src/cpu/static_inst.cc: src/cpu/static_inst.hh: src/cpu/thread_state.hh: src/dev/alpha_console.cc: src/dev/ns_gige.cc: src/dev/sinic.cc: src/dev/tsunami_cchip.cc: src/kern/kernel_stats.cc: src/kern/kernel_stats.hh: src/kern/linux/events.cc: src/kern/linux/events.hh: src/kern/system_events.cc: src/kern/system_events.hh: src/kern/tru64/dump_mbuf.cc: src/kern/tru64/tru64.hh: src/kern/tru64/tru64_events.cc: src/kern/tru64/tru64_events.hh: src/mem/vport.cc: src/mem/vport.hh: src/sim/faults.cc: src/sim/faults.hh: src/sim/process.cc: src/sim/process.hh: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: src/sim/syscall_emul.cc: src/sim/syscall_emul.hh: src/sim/system.cc: src/cpu/thread_context.hh: src/sim/system.hh: src/sim/vptr.hh: Change ExecContext to ThreadContext. --HG-- rename : src/cpu/exec_context.hh => src/cpu/thread_context.hh extra : convert_revision : 108bb97d15a114a565a2a6a23faa554f4e2fd77e
2006-05-31Updated Authors from bk prs infoAli Saidi
--HG-- extra : convert_revision : 77f475b156d81c03a2811818fa23593d5615c685
2006-05-29Create a new CpuEvent class that has a pointer to an execution context in ↵Ali Saidi
the object and places itself on a global list so so the events can be migrated on cpu switches. Create a new wrapper classe called CpuEventWrapper that works like the old wrapper class but calls the function with the xc parameter Use new CpuEventWrapper class from tick compare events on sparc src/arch/sparc/regfile.hh: Use new CpuEventWrapper class from tick compare events src/arch/sparc/ua2005.cc: Move definition to to a fullsystem only file, since it is. src/cpu/base.cc: On switch from one cpu to another CpuEvent::replaceExecContext() needs to be called on all (oldxc,newxc) pairs. --HG-- extra : convert_revision : eecf4540427cc0ddf75e19a3371cf32b56cba0f5
2006-05-29split off fullsystem and se iprs into two functions to remove lots of #ifsAli Saidi
setup all initialization stuff for UA2005 Setup fullsys build options Start to make fullsystem compile src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: RCS to BitKeeper src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: Add support for doing virtual to physical translation using the in-memory page table src/arch/sparc/vtophys.cc: a tad bit of error checking src/arch/sparc/vtophys.hh: Cleanup of full-system global variables, primarily in simple_cpu.cc, to allow multi-system simulations. (Multiple systems not yet yested though.) Also changes to build sim_smt in full-system mode (though with only SimpleCPU and not the full timing CPU for now). Still to do: minimize changes in SimpleCPU code between full-system and application modes... way too many ifdefs there. Much of the full-system stuff moved into SimpleCPU should be put in a new System object to allow multiprocessor simulations. Converted last remaining modules from C to C++ (mostly in /old). Renamed all .c files to .cc and a few .h files to .hh. Renamed architecture-specific files in arch/$TARGET from $TARGET.{cc,hh,def} to machine.{cc,hh,def} to get rid of pointless intermediate files in object directory. Split exo-specific definitions out of machine.hh into machine_exo.h. Specifics: In machine.def, null resource descriptors must be FUClamd_NA (and not NA) to pass C++ type checking. Enhanced error checking/reporting in bas src/arch/sparc/vtophys.cc: - Get rid of my String class, the Vector class, the bitvector class, and my doubly linked list class. - Convert tokenize, to_number (formerly StringToNumber) and eat_white to function on stl strings. - Change most cases of char * and const char * to string, or const string & - Some formatting and style nits, but not too many. src/arch/sparc/vtophys.cc: simplify src/arch/sparc/vtophys.cc: Renamed SimpleCPU::(read|write)_(byte|half|word|qword) to just read & write, overloaded on the type of the 'data' argument. Merged the full-system and non-full-system implementations of these eight original functions into two common template functions. To support this, also renamed (read|write)[1248] on memory_object and derivatives to just read & write, again overloaded on the type of the 'data' argument. Many of these functions could now be condensed into a few template functions (though with a level of indirection so that the interface can remain virtual). I did not do that though. src/arch/sparc/vtophys.cc: First pass at compiling with gcc 3.x. Lots of "std::" in header files, "using namespace std" in source files. (Note policy of not putting "using" statements in headers or before includes in sources.) Still not able to compile with gcc 3.2. Errors: - Can't create an ifstream from a file descriptor anymore (breaks IniFile). - "`class MSHR::MSHRegister' is private" errors in mshr.cc and prefetch_cache.cc: not clear why since it's in the public part of the class declaration. - cpu.cc:879: can't match a reference and 0 (specifically "no match for `bool ? SimObjectParam<PipeTrace*>& : int' operator") - pipetrace.cc: "invalid conversion from `int' to `std::_Ios_Fmtflags'" Warnings: - strstream now deprecated... needs some rewriting in sat_counter.hh and hybrid_pred.hh (need to get all that code out of the headers anyway) - trace.hh macro problem: cpp now says 'pasting "::" and "Event" does not give a valid preprocessing token' - major "implicit typename" issues in base/sized.hh src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: Implement some interval statistics for full system mode. Create a callpal function that is called when a callpal occurs so it's easier to manipulate the statics. Rework the vtophys stuff to make it a bit cleaner. src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: Get rid of almost all old-style object names. This commit is equivalent to running the following script on the current head: #! /bin/sh find \( -name '*.cc' -o -name '*.hh' \) -exec perl -pi -e '\ s/\bmemory_object\b(?!\.hh)/FunctionalMemory/g;\ s/\bvirtual_memory\b(?!\.hh)/VirtualMemory/g;\ s/\bmain_memory\b(?!\.hh)/MainMemory/g;\ s/\bphysical_memory\b(?!\.hh)/PhysicalMemory/g;\ s/\bspec_memory\b(?!\.hh)/SpeculativeMemory/g;\ s/\bMemObj\b(?!\.hh)/TimingMemObj/g;\ s/\bmemory_translation\b(?!\.hh)/AddressTranslator/g;\ s/\balpha_tlb\b(?!\.hh)/AlphaTlb/g;\ s/\balpha_itb\b(?!\.hh)/AlphaItb/g;\ s/\balpha_dtb\b(?!\.hh)/AlphaDtb/g;\ s/\bmemory_controller\b(?!\.hh)/MemoryController/g;\ s/\bstorebuffer_t\b(?!\.hh)/StoreBuffer/g;\ s/\bstorebuffer_entry_t\b(?!\.hh)/StoreBufferEntry/g;\ s/\bcreate_vector_t\b(?!\.hh)/CreateVector/g;\ s/\bcv_spec_state\b(?!\.hh)/CreateVecSpecState/g;\ s/\bspec_state_list\b(?!\.hh)/SpecStateList/g;\ s/\bdyn_inst_t\b(?!\.hh)/DynInst/g;' {} \; src/arch/sparc/vtophys.cc: since cprintf properly deals with 64-bit types, stop using FMT* as much as possible src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: Change byte_t etc. to C99 standard int8_t etc. Other than old/host.h, all other changes were produced by this script: #! /bin/sh find \( -name '*.cc' -o -name '*.hh' -o -name '*.c' -o -name '*.h' -o -name 'machine.def' \) -exec perl -pi -e '\ s/\bbyte_t\b(?!\.hh)/uint8_t/g;\ s/\bsbyte_t\b(?!\.hh)/int8_t/g;\ s/\bhalf_t\b(?!\.hh)/uint16_t/g;\ s/\bshalf_t\b(?!\.hh)/int16_t/g;\ s/\bword_t\b(?!\.hh)/uint32_t/g;\ s/\bsword_t\b(?!\.hh)/int32_t/g;\ s/\bqword_t\b(?!\.hh)/uint64_t/g;\ s/\bsqword_t\b(?!\.hh)/int64_t/g;\ s/\bbool_t\b(?!\.hh)/bool/g;\ s/\bdfloat_t\b(?!\.hh)/double/g;\ s/\bsfloat_t\b(?!\.hh)/float/g;' {} \; src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: Add CVS Id tags src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: Massive renaming to (almost) eliminate all md_* and MD_* names in preparation for total exorcism of machine.def. Most of the changes in this commit were performed with the following perl script (perl -pi <script> <files>). A small amount of manual fixup was needed to (mostly getting rid of the Addr typedefs in the various memory objects now that the former md_addr_t has that name). # rename machine-dependent types and constants (will be moving into ISA traits object) s/md_addr_t/Addr/g; s/md_intreg_t/IntReg/g; s/md_gpr_t/IntRegFile/g; s/md_fpreg_t/FloatReg/g; s/md_fpr_t/FloatRegFile/g; s/md_ctrlreg_t/MiscReg/g; s/md_ctrl_t/MiscRegFile/g; s/md_ipr_t/InternalProcReg/g; s/md_anyreg_t/AnyReg/g; s/md_inst_t/MachInst/g; s/regs_t/RegFile/g; # manually fix declaration in old/regs.h and a few forward decls s/struct RegFile/RegFile/g; s/MD_NUM_IREGS/NumIntRegs/g; s/MD_NUM_FREGS/NumFloatRegs/g; s/MD_NUM_CREGS/NumMiscRegs/g; s/MD_IPR_NUM/NumInternalProcRegs/g; s/MD_TOTAL_REGS/TotalNumRegs/g; s/MD_REG_ZERO/ZeroReg/g; src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: New ISA description system. No more machine.def! Instructions are now decoded into StaticInst objects, and all static instruction properties (including execution behavior) are associated with those objects. Extended documentation in progress. Currently supports Alpha only; PISA will not compile. Use END_OF_MACHINE_DOT_DEF tag to extract previous version. src/arch/sparc/vtophys.cc: get rid of MD_IPR_foo and call it IPR_foo add some comments to describe what the various PALtemp registers do formatting src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: license src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: a little style src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: Add attribution to license. src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: Make include paths explicit. src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: CopyData and CopyString moved from kernel.cc to vtophys.cc kernel.cc and kernel.hh moved to kern/tru64 src/arch/sparc/vtophys.hh: Include isa_traits.hh for Addr src/arch/sparc/vtophys.cc: formatting fixes src/arch/sparc/vtophys.cc: fix up vtophys to deal with translations if there is no ptbr, and to deal with PAL addresses add ptomem which is just a wrapper for dma_addr src/arch/sparc/vtophys.hh: add ptomem which is a wrapper for dma_addr with the same usage as vtomem src/arch/sparc/vtophys.cc: Fix to remote debugger while in PAL code src/arch/sparc/vtophys.cc: Remote an old hack that is now unnecessary src/arch/sparc/vtophys.cc: Removed buggy code that tries to fix PAL addresses (may cause problems while trying to debug in PAL code, but that should do this fix outside of vtophys) src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: Updated Copyright src/arch/sparc/vtophys.cc: added back some code andrew removed and couldn't remember why. src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: rename CopyData to CopyOut and implement CopyIn to copy data from the simulator into the simulatee src/arch/sparc/vtophys.cc: fixed a bad merge from linux<->tru64 src/arch/sparc/vtophys.cc: Check max address pal can be at so we don't do the wrong conversion if gdb asks for an unaligned access. src/arch/sparc/vtophys.cc: PGOFSET -> ALPHA_PGOFSET to avoid include file problems src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: in the arch/alpha directory we should use arch/alpha, not targetarch. sort includes while we're here. src/arch/sparc/vtophys.cc: use new constants, functions and structs to clean up the vtophys code. src/arch/sparc/vtophys.hh: Clean up a little bit and make the protypes match new changes. src/arch/sparc/vtophys.cc: deal with isa addition src/arch/sparc/vtophys.cc: shuffle files around for new directory structure src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: Remove RCS Id string src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: Update copyright dates and author list src/arch/sparc/vtophys.cc: Added a using directive for AlphaISA src/arch/sparc/vtophys.hh: Added the AlphaISA namespace specifier where needed src/arch/sparc/vtophys.hh: Made Addr a global type src/arch/sparc/vtophys.cc: Change access to the IPR to go through the XC. src/arch/sparc/vtophys.cc: Avoid directly accessing objects within the XC. src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: fixed for new memory system put in namespace AlphaISA src/arch/alpha/vtophys.cc: src/arch/alpha/vtophys.hh: Remove authors from copyright. src/arch/sparc/vtophys.cc: bk cp alpha/vtophys.cc sparc/vtophys.cc src/arch/sparc/vtophys.hh: bk cp alpha/vtophys.hh sparc/vtophys.hh src/arch/sparc/SConscript: remove fullsystem files that don't exist src/arch/sparc/isa_traits.hh: split off fullsystem and se iprs into two functions to remove lots of #ifs src/arch/sparc/regfile.hh: split off fullsystem and se iprs into two functions to remove lots of #ifs setup all initialization stuff for UA2005 src/arch/sparc/system.cc: src/arch/sparc/system.hh: Add system level tick storage to make stick be syncronized across multiple processors src/arch/sparc/vtophys.hh: start to create a vtophys for Sparc src/base/loader/symtab.hh: Addr is defined in sim/host.hh --HG-- extra : convert_revision : ae4658e6bc2e2b51d7fb1c711d069ffe99e1377d