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path: root/src/arch/sparc
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2006-11-10The reset function of the MiscRegFile really resets it now. This function is ↵Gabe Black
called from the class's constructor. --HG-- extra : convert_revision : 4e7a40ffe0a9a71fd1b2b171d9c0dcac50e1a1fe
2006-11-10Set the ASI register to be something explicitly so that simulation is ↵Gabe Black
deterministic. --HG-- extra : convert_revision : 38cd06f946fc0cc22288f71f567e77ce8fdfea99
2006-11-10Fix up instructions to read and write control registers, and got rid of the ↵Gabe Black
control register fields which won't work on a big endian host. --HG-- extra : convert_revision : 1b518873b6e1a073b58cbe27642537d5ae3a604d
2006-11-09Moved the Alpha MiscRegFile into it's own file, and got rid of the Alpha ↵Gabe Black
specific DepTag constants. --HG-- extra : convert_revision : e4af5e2fb2a6953f8837ad9bda309b7d6fa7abfb
2006-11-09Fix a couple uninitialized variables.Gabe Black
--HG-- extra : convert_revision : d17d28a9520524e5f56bd79beb9b2be6ce76a22f
2006-11-09Get SPARC to the point that it starts running. Add ability to load the ROM ↵Ali Saidi
bin files, cleanup lockstep printing a bit Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work. SConstruct: Add TARGET_ISA to the list of environment variables that end up in the build_env for python configs/common/FSConfig.py: add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now src/SConscript: add a raw file object, at least until we get more info about how to compile openboot properly src/arch/sparc/system.cc: src/arch/sparc/system.hh: add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM src/base/loader/object_file.cc: src/base/loader/object_file.hh: add option to try raw when nothing works src/cpu/exetrace.cc: cleanup lockstep printing a little bit src/cpu/m5legion_interface.h: change the instruction to be 32 bits because it is src/mem/physical.cc: fix assert that doesn't work if memory starts somewhere above 0 src/python/m5/objects/BaseCPU.py: Add if statement to choose between sparc tlbs and alpha tlbs src/python/m5/objects/System.py: Add a sparc system that sets the rom addresses correctly src/python/m5/params.py: add the ability to add Addr() together --HG-- extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af
2006-11-08First cut at full blown SPARC faults. There are a few details that are missing.Gabe Black
--HG-- extra : convert_revision : 8023db1479cb9bf99fc9edfeb521c4e5b581f895
2006-11-08Move the check to see if you're in user mode into the isa directory.Gabe Black
--HG-- extra : convert_revision : b5b7cdf4a5e5e54228c592093516bf18d0f7dbe6
2006-11-08Sorted faults by the trap type constant, expanded their names, added in new ↵Gabe Black
faults for ua2005, and commented out ones which are apparently dropped. --HG-- extra : convert_revision : 32bd0c3a75d7c036ad4a3cb0bc1c32e0b6cb3d87
2006-11-08Fix for slightly mangled merge.Gabe Black
--HG-- extra : convert_revision : 1dea04ca222dd423c3d462114bc1c65afa52825d
2006-11-08Merge zeep.eecs.umich.edu:/home/gblack/m5/newmemGabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops src/arch/sparc/faults.hh: Hand merged. --HG-- extra : convert_revision : 1bcefe47fa98e878a0dfbcfa5869b5b171927911
2006-11-08Major clean up of the fault code.Gabe Black
--HG-- extra : convert_revision : eb7e016a127417cbb0e1e2c733b17f82469c2f24
2006-11-08The new global level is computed with min, not max.Gabe Black
--HG-- extra : convert_revision : 6339c82d3655694445c3eb43e467b9aa6b4c8224
2006-11-08Changed the getReg and setReg functions so that they work like netbsd. ↵Gabe Black
Apparently, gdb expects to do single stepping on its own, so those functions panic for SPARC. acc still needs to be implemented. --HG-- extra : convert_revision : c6e98e37b8ab3d6f8d6b3cd2c961faa65b08a179
2006-11-08Put the ProcessInfo and StackTrace objects into the ISA namespaces.Gabe Black
--HG-- extra : convert_revision : 1626703583f02a1c9823874290462c1b6bdb6c3c
2006-11-08Stubs for SPARC's tlbsGabe Black
--HG-- extra : convert_revision : ba08da78693cc6f59f7358134f121f471910dbf6
2006-11-08Replaced getArg with a SPARC implementation.Gabe Black
--HG-- extra : convert_revision : ba31171a81b6c46de2997de2701d35fcf8c614b7
2006-11-07Put kernel_stats back into arch.Gabe Black
--HG-- rename : src/kern/alpha/idle_event.cc => src/arch/alpha/idle_event.cc rename : src/kern/alpha/idle_event.hh => src/arch/alpha/idle_event.hh rename : src/kern/alpha/kernel_stats.cc => src/arch/alpha/kernel_stats.cc rename : src/kern/alpha/kernel_stats.hh => src/arch/alpha/kernel_stats.hh rename : src/kern/sparc/kernel_stats.hh => src/arch/sparc/kernel_stats.hh rename : src/kern/base_kernel_stats.cc => src/kern/kernel_stats.cc rename : src/kern/base_kernel_stats.hh => src/kern/kernel_stats.hh extra : convert_revision : 42bd3e36b407edbd19b912c9218f4e5923a15966
2006-11-07A dummy implementation of stacktrace.cc to clear up linker errors.Gabe Black
--HG-- extra : convert_revision : ea1e54a529ad7ae4a6564dd6fb47c31fb0573adf
2006-11-07Arguments class for SPARC. This is basically just a copy of Alpha'sGabe Black
--HG-- extra : convert_revision : 9df68973c63d5ff256d6de485e8d918c454c8ff1
2006-11-07Added a stub implementation of fixFuncEventAddr to get past linker errors.Gabe Black
--HG-- extra : convert_revision : 24ab1789496c5fae6c0992db2d521ea02354ee90
2006-11-07The normal spill and fill faults only need to behave specially in SE.Gabe Black
--HG-- extra : convert_revision : 4d4b866699e3450b88418822fc198411ee3d831a
2006-11-07Added in alot of missing source files.Gabe Black
--HG-- extra : convert_revision : 335b458d195a00dac3d04e92fe9df915e660538f
2006-11-07Broke remote_gdb into a base class and architecture specific derived classes.Gabe Black
--HG-- extra : convert_revision : 8c528fab56a95b8245ad0f2572d62bb556ce0dde
2006-11-06Merge zizzer.eecs.umich.edu:/bk/newmem/Gabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops src/SConscript: SCCS merged --HG-- extra : convert_revision : f130c8a2d33f58d857e5d5a02bb9698c1bceb23b
2006-11-06Stub for SPARC interrupt handling object.Gabe Black
--HG-- extra : convert_revision : 7257e3387c01e84e5a1018a9cdcc09a79edfa934
2006-11-06Remote GDB support has been changed to use inheritance. Alpha should work, ↵Gabe Black
but isn't tested. Other architectures will not. --HG-- extra : convert_revision : fc7e1e73e2f3b1a4ab9905a1eb98c5f07c6c8707
2006-11-04fixes so that M5 will compile under solarisAli Saidi
SConstruct: Add check to see if we need to include libsocket src/arch/sparc/floatregfile.cc: src/arch/sparc/intregfile.cc: use memset rather than bzero and include the appropriate headerfile src/base/pollevent.cc: If we're compling under solaris we need sys/file.h src/base/random.cc: src/base/random.hh: solaris doesn't have random(), so use rint with the correct rounding mode if we're compiling on solaris src/base/stats/flags.hh: u_int32_t?? src/base/time.hh: grab the timersub() define from freebsd since it doesn't exist in solaris src/cpu/inst_seq.hh: we don't need to include stdint here src/sim/byteswap.hh: the method to detect endianness on Solaris is a little more complex... --HG-- extra : convert_revision : 6b7db0e900e7bccfc250d65c125065f27280dda1
2006-11-03Make things compile in SE again.Gabe Black
--HG-- extra : convert_revision : cf7faf5001b31d61c61ddce2386d61c919075800
2006-11-03Use a PowerOnReset to initialize the cpu.Gabe Black
--HG-- extra : convert_revision : 9e65af095c37c7c67db377424d2d4363fa8065f9
2006-11-03Calling syscalls from within the trap instruction's invoke method won't work ↵Gabe Black
because apparently you need an xc for that and not a tc. Cleaned up the TrapInstruction fault in light of this. --HG-- extra : convert_revision : 1805c9244cfd62d0ee7862d8fd7c9983e00c5747
2006-11-03Gutted out the old Alpha stuff.Gabe Black
--HG-- extra : convert_revision : 6767dc1305a58e3e7eb0ee909d54768e51744927
2006-11-03Added a stub initCPU function. This would be a good place to force in a ↵Gabe Black
PowerOnReset fault to kick start the CPU. --HG-- extra : convert_revision : 79e1fa2ef40e326682069639e260db255fd29d93
2006-11-03Compilation fixes.Gabe Black
--HG-- extra : convert_revision : 44d67a3bb95f875f17586499aa4a04268aa2fd46
2006-11-03Add the syscall number as the second parameter for the trap fault. This ↵Gabe Black
could be improved and syscalls could be called from the trap's invoke method. --HG-- extra : convert_revision : 127a3673a076110fb3605c0fbc93e8d7e9fec84b
2006-11-03Add an invoke function for PowerOnResetGabe Black
--HG-- extra : convert_revision : a1cdd35c74f6e85f42a04061b466ec7617da8ac2
2006-11-03Move around misc reg codeGabe Black
src/arch/sparc/faults.cc: Moved some code here from miscregfile.cc src/arch/sparc/miscregfile.cc: Moved code from here to faults.cc, and merged (read|set)MiscRegWithEffect and it's FS version from ua2005.cc src/arch/sparc/miscregfile.hh: readFSRegWithEffect is no longer a seperate function, and is instead done in the main readRegWith Effect. --HG-- extra : convert_revision : 0b45f0f78e83929b32ddd2f443c8b1dbf9bc04fb
2006-11-03removed ua2005.cc since it's been obsorbed into the miscregfile, and added ↵Gabe Black
system.cc --HG-- extra : convert_revision : 2a124adcefe0d15860632a05e8788d3fd34008c2
2006-11-03Fixed a commentGabe Black
--HG-- extra : convert_revision : bebc701508e1d38ee74a07377c634d5e46e89abe
2006-11-01Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register ↵Gabe Black
file functions to not take faults --HG-- extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
2006-10-31Get rid of old, commented out code.Gabe Black
--HG-- extra : convert_revision : 46e9f26917efab642b80ea9e4303ec95d43d935e
2006-10-29Move the mem classes into util.isa so that multiple inheritance can be used ↵Gabe Black
in the future for micro insts. --HG-- extra : convert_revision : c71faa5e43b56ed15d00ed5fd57c020d1c845445
2006-10-29Fix when the IsDelayedCommit flag is set.Gabe Black
--HG-- extra : convert_revision : ab6cd69f82b2013d66a91beaa3e39d8f417a9251
2006-10-29Bring casa and casxa up to dateGabe Black
src/arch/sparc/isa/decoder.isa: Fix up the casa and casxa instructions. src/arch/sparc/isa/formats/formats.isa: This is handled in loadstore.isa now src/arch/sparc/isa/formats/mem/basicmem.isa: src/arch/sparc/isa/formats/mem/blockmem.isa: Renamed doSplitExecute to doDualSplitExecute. This differentiates between the version that does both a register and immediate version, and one that just does a register version. src/arch/sparc/isa/formats/mem/mem.isa: The cas format is handled in loadstore.isa as well now. src/arch/sparc/isa/formats/mem/util.isa: Reorganized things a bit to better support cas --HG-- extra : convert_revision : 12411e89e763287e52f9825bf7a417b263c1037f
2006-10-29Fixed ldstub to use the right format, and made the load/store operations use ↵Gabe Black
the integer microcode register. --HG-- extra : convert_revision : 7df5bd4bbe8a2607c7d2b4799826831d6a440926
2006-10-29Add an integer microcode register.Gabe Black
--HG-- extra : convert_revision : f23dbfdfe44e8e6cdd6948000669ad4f743b9fb4
2006-10-27Got rid of some outdated comments.Gabe Black
--HG-- extra : convert_revision : 30fa768c4a934cf5f9dc0ad84e0e421327ccbed3
2006-10-27Made the regfile compatible with the new definitions in MiscRegFileGabe Black
--HG-- extra : convert_revision : d63ea6fb1e549e737204ee6653c06f89ec5e43ef
2006-10-27Clean up MiscRegFileGabe Black
--HG-- extra : convert_revision : 3bc792596c99df3a5c2c82da58b801a63ccf6ddb
2006-10-26Reorganized the MiscRegFileGabe Black
--HG-- extra : convert_revision : 088112c9b8a4ea09c8015da5a0b65ed2fc9398d2
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