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2006-12-16Made changes to CWP be non speculative.Gabe Black
--HG-- extra : convert_revision : 43899bc97061c33e67a53179c23e46b079118117
2006-12-16Changes to the isa_parser and affected files to fix an indexing problem with ↵Gabe Black
split execute instructions and miscregs aliasing with integer registers. src/arch/isa_parser.py: Rearranged things so that classes with more than one execute function treat operands properly. 1. Eliminated the CodeBlock class 2. Created a SubOperandList 3. Redefined how InstObjParams is constructed To define an InstObjParam, you can either pass in a single code literal which will be named "code", or you can pass in a dictionary of code snippets which will be substituted into the Templates. In order to get this to work, there is a new restriction that each template has only one function in it. These changes should only affect memory instructions which have regular and split execute functions. Also changed the MiscRegs so that they use the instrunctions srcReg and destReg arrays. src/arch/sparc/isa/formats/basic.isa: src/arch/sparc/isa/formats/branch.isa: src/arch/sparc/isa/formats/integerop.isa: src/arch/sparc/isa/formats/mem/basicmem.isa: src/arch/sparc/isa/formats/mem/blockmem.isa: src/arch/sparc/isa/formats/mem/util.isa: src/arch/sparc/isa/formats/nop.isa: src/arch/sparc/isa/formats/priv.isa: src/arch/sparc/isa/formats/trap.isa: Rearranged to work with new InstObjParam scheme. src/cpu/o3/sparc/dyn_inst.hh: Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays. Also changed the names of the other accessors so that they have the suffix "Operand" if they use those arrays. src/cpu/simple/base.hh: Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays. --HG-- extra : convert_revision : c91e1073138b72bcf4113a721e0ed40ec600cf2e
2006-12-07Make branches handle the lack of a symbol table or the lack of a symbol ↵Gabe Black
gracefully. --HG-- extra : convert_revision : 7bb16405999b86f9fa082a6d44da43d346edc182
2006-12-07Change how Page Faults work in SPARC. It now prints the faulting address, ↵Gabe Black
and panics instead of fatals. This isn't technically what it should do, but it makes gdb stop at the panic rather than letting m5 exit. --HG-- extra : convert_revision : 3b14c99edaf649e0809977c9579afb2b7b0d72e9
2006-12-06Change to use -return_value.value like other implementations.Gabe Black
--HG-- extra : convert_revision : 513422c1c8c24f3662e6a423d13ee033424aa44b
2006-12-06Some changes for misc regs which were changed into unofficial integer ↵Gabe Black
registers, and moved the flattenIndex function into the register file. --HG-- extra : convert_revision : 6b797c793a6c12c61a23f0f78a1ea1c88609553e
2006-12-06Reorganize the includes and add an include for misc.hh.Gabe Black
--HG-- extra : convert_revision : 484b2d07a1e8b3879c35d80bf16b73fd0cc9be1f
2006-12-06Added some debug output, and made sure not to accidentally ask for the ↵Gabe Black
result of a store conditional. --HG-- extra : convert_revision : d36ff9e2343fdf78a3bc16a1348975fdba5c55e2
2006-12-06Some basic fix ups, and CWP is no longer set explicitly.Gabe Black
--HG-- extra : convert_revision : 1dde5594a2bcfd9fb5ad974360b3dc035f1624e5
2006-12-06Changed the integer register file to work with flattened indices.Gabe Black
--HG-- extra : convert_revision : c5153c3c712e5d18b5233e1fd205806adcb30654
2006-12-05Move the SyscallReturn class into sim/syscallreturn.hh. Also move some ↵Gabe Black
miscregs into the integer register file so they get renamed. src/arch/alpha/syscallreturn.hh: src/arch/mips/syscallreturn.hh: src/sim/syscallreturn.hh: Move the SyscallReturn class into sim/syscallreturn.hh src/arch/sparc/faults.cc: src/arch/sparc/isa/operands.isa: src/arch/sparc/isa_traits.hh: src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: src/arch/sparc/process.cc: src/arch/sparc/sparc_traits.hh: Move some miscregs into the integer register file so they get renamed. --HG-- extra : convert_revision : df5b94fa1e7fdca34816084e0a423d6fdf86c79b
2006-11-24Initial changes to get O3 working with SPARCGabe Black
src/arch/sparc/process.cc: MachineBytes doesn't exist any more. src/arch/sparc/regfile.cc: Add in the miscRegFile for good measure. src/cpu/o3/isa_specific.hh: Add in a section for SPARC src/cpu/o3/sparc/cpu.cc: src/cpu/o3/sparc/cpu.hh: src/cpu/o3/sparc/cpu_builder.cc: src/cpu/o3/sparc/cpu_impl.hh: src/cpu/o3/sparc/dyn_inst.cc: src/cpu/o3/sparc/dyn_inst.hh: src/cpu/o3/sparc/dyn_inst_impl.hh: src/cpu/o3/sparc/impl.hh: src/cpu/o3/sparc/params.hh: src/cpu/o3/sparc/thread_context.cc: src/cpu/o3/sparc/thread_context.hh: Sparc version of this file. --HG-- extra : convert_revision : 34bb5218f802d0a1328132a518cdd769fb59b6a4
2006-11-24Rename this function.Gabe Black
--HG-- extra : convert_revision : 57ea1e1d3b75e35abb3310d392ec70086fff699a
2006-11-24Fix weird type modifier.Gabe Black
--HG-- extra : convert_revision : 7372b7a92b3c9d05388acb43ba58ada18464fa24
2006-11-24Fix an include problem.Gabe Black
--HG-- extra : convert_revision : 89be55bd3f4f9b452a680a98b69ce42b80546769
2006-11-23Fixes to the isa description.Gabe Black
src/arch/sparc/isa/base.isa: Fix a constant. src/arch/sparc/isa/decoder.isa: Made carry calculation more consistent. src/arch/sparc/isa/operands.isa: Use the right constant. --HG-- extra : convert_revision : 25b3a09ff20d4b8e1a95ee8a983d14ef3cfe73bb
2006-11-22Moved some constants from isa_traits.hh to the reg file headers.Gabe Black
--HG-- extra : convert_revision : 378b2d9791e6282539900a2261ad2275d726b4be
2006-11-22Merge zizzer:/bk/sparcfsGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : 75f3398e38e18eb1f8248e23708d7a8d8cce0fc5
2006-11-20Make sure only real bits of pstate can be set.Gabe Black
--HG-- extra : convert_revision : 8707bbed2aeb80613f86503e92b63853767adaa9
2006-11-20Set the pstate.priv bit to 1 in hyperpriveleged mode. The description in the ↵Gabe Black
manual of what happens during a trap says it should be 0, and other places say it doesn't matter. --HG-- extra : convert_revision : 9ecb6af06657e936a208cbeb8e4a18305869b949
2006-11-20Add in rom/rams for the nvram, hypervisor description, and partition ↵Gabe Black
description. --HG-- extra : convert_revision : a49de5fcfbea307c971964b8a68b95eb5d9a2bf4
2006-11-16Implement current working directory for LiveProcessesNathan Binkert
--HG-- extra : convert_revision : a2d3cf29ab65c61af27d82a8c421a41a19fd5aeb
2006-11-16Merge zower.eecs.umich.edu:/home/gblack/m5/newmemmemopsGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : 74b2352b8f088e38cd1ecf3a8233b45df0476d93
2006-11-16Fixes for SPARC_FSGabe Black
configs/common/FSConfig.py: Make a SPARC system create an IO bus. src/python/m5/objects/T1000.py: Create a T1000 platform src/arch/sparc/miscregfile.cc: Initialize the strand status register to the value legion provides. src/cpu/exetrace.cc: Truncate an ExtMachInst to a MachInst before comparing with Legion. --HG-- extra : convert_revision : e4189b572a5297e8362f5bd26d87b74736c8e5f1
2006-11-14Merge zizzer.eecs.umich.edu:/bk/newmem/Gabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops --HG-- extra : convert_revision : 966246877ac1f1e6c2675d413b0b405cccfecbeb
2006-11-14interrupts.hh:Lisa Hsu
make a likewise updateIntrInfo for Sparc that's blank so it doesn't fart on build src/arch/sparc/interrupts.hh: make a likewise updateIntrInfo for Sparc that's blank so it doesn't fart on build --HG-- extra : convert_revision : 5f469d0cf897479b42703104cd801a8ef923fcae
2006-11-14Set hpstate to be what I'm assuming Legion is.Gabe Black
--HG-- extra : convert_revision : 0be66513cb0cff07c0c2b50c97c1ea74d52b0dc9
2006-11-14Make sure a POR doesn't clobber the value of the hpstate.Gabe Black
--HG-- extra : convert_revision : 4504f08fd94792819bd4419bbd2e0ebd1d7f29e9
2006-11-14Fix up the disassembly a little.Gabe Black
--HG-- extra : convert_revision : 7bdf68f445b79b1b5dbcdfa5fa1005c68d03724c
2006-11-11Fix for CAS so that it knows about all the possible code in the constructor.Gabe Black
--HG-- extra : convert_revision : 863d395f8e7c8ee2aec708ffcef842317ec9a89b
2006-11-10fix endian issues with condition codesAli Saidi
use memcpy instead of bcopy s/u_int32_t/uint32_t/g fixup endian code to work with solaris hack to make sure htole() works... Nate, have a good idea to fix this? src/arch/sparc/faults.cc: set the reset address to be 40 bits. Makes PC printing easier at least for now. src/arch/sparc/isa/base.isa: fix endian issues with condition codes src/arch/sparc/tlb.hh: add implemented physical addres constants src/arch/sparc/utility.hh: add tlb.hh to utilities src/base/loader/raw_object.cc: add a symbol <filename>_start to the symbol table for binaries files src/base/remote_gdb.cc: use memcpy instead of bcopy src/cpu/exetrace.cc: clean up printing a bit more src/cpu/m5legion_interface.h: add tons to the shared interface src/dev/ethertap.cc: s/u_int32_t/uint32_t/g src/dev/ide_atareg.h: fixup endian code to work with solaris src/dev/pcidev.cc: src/sim/param.hh: hack to make sure htole() works... --HG-- extra : convert_revision : 4579392184b40bcc1062671a953c6595c685e9b2
2006-11-10Elaborated on the tlb stubs so that they just set the physical address to ↵Gabe Black
the virtual address. --HG-- extra : convert_revision : 41478abc4d21d504420f6842338675c0767f7cf9
2006-11-10Fixed up DepTags a little. I think NumMicroIntRegs shouldn't be added to ↵Gabe Black
Ctrl_Base_DepTag. --HG-- extra : convert_revision : 2ebb3eb781441ba936c8d8bb1f42e4c0840aff2e
2006-11-10Added StrandStsReg operand.Gabe Black
--HG-- extra : convert_revision : 51be41716ed9fe0e99e53f2341ad5651a525055a
2006-11-10Put in provisions for rd, rdpr, rdhpr, wr, wrpr, and wrhpr to disassemble ↵Gabe Black
properly. --HG-- extra : convert_revision : f2cad8a5879999438ba9b05f15a91320e7a4cc4a
2006-11-10Made the annul of unconditional conditional branches behave properly, added ↵Gabe Black
code to read and write the strand_sts_reg, and made restored a Priv instruction. --HG-- extra : convert_revision : 386512215f7243d230717c369217f8d2f9ada935
2006-11-10Fixed up the code that prints out registers to take into account microregisters.Gabe Black
--HG-- extra : convert_revision : 6809de467e4500ce34447c0544caf0ba04af81e7
2006-11-10Tweaked debug output.Gabe Black
--HG-- extra : convert_revision : cd33b7c1ebdbefd42f18c1435b2519d06d9914a6
2006-11-10Touched up faults, and made POR actually do something.Gabe Black
--HG-- extra : convert_revision : 38951352edbfc423fb6767a9aac49a703578c0ac
2006-11-10The reset function of the MiscRegFile really resets it now. This function is ↵Gabe Black
called from the class's constructor. --HG-- extra : convert_revision : 4e7a40ffe0a9a71fd1b2b171d9c0dcac50e1a1fe
2006-11-10Set the ASI register to be something explicitly so that simulation is ↵Gabe Black
deterministic. --HG-- extra : convert_revision : 38cd06f946fc0cc22288f71f567e77ce8fdfea99
2006-11-10Fix up instructions to read and write control registers, and got rid of the ↵Gabe Black
control register fields which won't work on a big endian host. --HG-- extra : convert_revision : 1b518873b6e1a073b58cbe27642537d5ae3a604d
2006-11-09Moved the Alpha MiscRegFile into it's own file, and got rid of the Alpha ↵Gabe Black
specific DepTag constants. --HG-- extra : convert_revision : e4af5e2fb2a6953f8837ad9bda309b7d6fa7abfb
2006-11-09Fix a couple uninitialized variables.Gabe Black
--HG-- extra : convert_revision : d17d28a9520524e5f56bd79beb9b2be6ce76a22f
2006-11-09Get SPARC to the point that it starts running. Add ability to load the ROM ↵Ali Saidi
bin files, cleanup lockstep printing a bit Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work. SConstruct: Add TARGET_ISA to the list of environment variables that end up in the build_env for python configs/common/FSConfig.py: add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now src/SConscript: add a raw file object, at least until we get more info about how to compile openboot properly src/arch/sparc/system.cc: src/arch/sparc/system.hh: add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM src/base/loader/object_file.cc: src/base/loader/object_file.hh: add option to try raw when nothing works src/cpu/exetrace.cc: cleanup lockstep printing a little bit src/cpu/m5legion_interface.h: change the instruction to be 32 bits because it is src/mem/physical.cc: fix assert that doesn't work if memory starts somewhere above 0 src/python/m5/objects/BaseCPU.py: Add if statement to choose between sparc tlbs and alpha tlbs src/python/m5/objects/System.py: Add a sparc system that sets the rom addresses correctly src/python/m5/params.py: add the ability to add Addr() together --HG-- extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af
2006-11-08First cut at full blown SPARC faults. There are a few details that are missing.Gabe Black
--HG-- extra : convert_revision : 8023db1479cb9bf99fc9edfeb521c4e5b581f895
2006-11-08Move the check to see if you're in user mode into the isa directory.Gabe Black
--HG-- extra : convert_revision : b5b7cdf4a5e5e54228c592093516bf18d0f7dbe6
2006-11-08Sorted faults by the trap type constant, expanded their names, added in new ↵Gabe Black
faults for ua2005, and commented out ones which are apparently dropped. --HG-- extra : convert_revision : 32bd0c3a75d7c036ad4a3cb0bc1c32e0b6cb3d87
2006-11-08Fix for slightly mangled merge.Gabe Black
--HG-- extra : convert_revision : 1dea04ca222dd423c3d462114bc1c65afa52825d
2006-11-08Merge zeep.eecs.umich.edu:/home/gblack/m5/newmemGabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops src/arch/sparc/faults.hh: Hand merged. --HG-- extra : convert_revision : 1bcefe47fa98e878a0dfbcfa5869b5b171927911
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