Age | Commit message (Collapse) | Author |
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undefined opcodes in impdep2 (which in SE is all of them) trap with an illegal_instruction exception.
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extra : convert_revision : dd7848d0685e4cc6f5fd5e3b846a3f70b62ee30a
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : 4105ebbeca59206bece27f229ee810d594fb4310
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util/m5/Makefile.alpha:
Clean up to make it a bit easier to muck with
util/m5/Makefile.alpha:
Make the makefile more reasonable
util/m5/Makefile.alpha:
Remove authors from copyright.
util/m5/Makefile.alpha:
Updated Authors from bk prs info
util/m5/Makefile.alpha:
bk cp Makefile Makefile.alpha
src/arch/sparc/tlb.cc:
Clean up the cache code a little bit and make sure the uncacbale bit is set when appropriate
src/arch/alpha/isa/decoder.isa:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
Rename AlphaPseudo -> PseudoInst since it's all generic
src/arch/sparc/isa/bitfields.isa:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/includes.isa:
src/arch/sparc/isa/operands.isa:
Add support for pseudo instructions in sparc
util/m5/Makefile.alpha:
util/m5/Makefile.sparc:
split off alpha make file and sparc make file for m5 app
util/m5/m5.c:
ivle and ivlb aren't used anymore
util/m5/m5op.h:
stdint seems like a more generic better fit here
util/m5/m5op_alpha.S:
move the op ids into their own header file since we can share them between sparc and alpha
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rename : util/m5/Makefile => util/m5/Makefile.sparc
rename : util/m5/m5op.S => util/m5/m5op_alpha.S
extra : convert_revision : 490ba2e8b8bc6e28bfc009cedec6b686b28e7834
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This basically involves moving the builder code outside of any
namespace. While we're at it, move a few braces outside of
a couple #if/#else/#endif blocks so it's easier to match up
the braces.
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extra : convert_revision : a7834532aadc63b0e0ff988dd5745049e02e6312
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src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
src/arch/sparc/arguments.hh:
move Copy* to vport since it's generic for all the ISAs
src/arch/sparc/isa_traits.hh:
the Solaris kernel sets up a virtual-> real mapping for all memory starting at SegKPMBase
src/arch/sparc/pagetable.hh:
add a class for getting bits out of the TteTag
src/arch/sparc/remote_gdb.cc:
add 32bit support kinda.... If its 32 bit
src/arch/sparc/remote_gdb.hh:
Add 32bit register offsets too.
src/arch/sparc/tlb.cc:
cleanup generation of tsb pointers
src/arch/sparc/tlb.hh:
add function to return tsb pointers for an address
make lookup public so vtophys can use it
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
write vtophys for sparc
src/base/bitfield.hh:
return a mask of bits first->last
src/mem/vport.cc:
src/mem/vport.hh:
move Copy* here since it's ISA generic
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extra : convert_revision : c42c331e396c0d51a2789029d8e232fe66995d0f
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extra : convert_revision : 5edf0ad492fe438d66bcf0ae469ef841cd71e157
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extra : convert_revision : 5bfe4b943ca5b3e30a7097a46cab4f93dadd714f
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conditional swaps as well
Add support for a twin 64 bit int load
Add Memory barrier and write barrier flags as appropriate
Make atomic memory ops atomic
src/arch/alpha/isa/mem.isa:
src/arch/alpha/locked_mem.hh:
src/cpu/base_dyn_inst.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/arch/alpha/types.hh:
src/arch/mips/types.hh:
src/arch/sparc/types.hh:
add a largest read data type for statically allocating read buffers in atomic simple cpu
src/arch/isa_parser.py:
Add support for a twin 64 bit int load
src/arch/sparc/isa/decoder.isa:
Make atomic memory ops atomic
Add Memory barrier and write barrier flags as appropriate
src/arch/sparc/isa/formats/mem/basicmem.isa:
add post access code block and define a twinload format for twin loads
src/arch/sparc/isa/formats/mem/blockmem.isa:
remove old microcoded twin load coad
src/arch/sparc/isa/formats/mem/mem.isa:
swap.isa replaces the code in loadstore.isa
src/arch/sparc/isa/formats/mem/util.isa:
add a post access code block
src/arch/sparc/isa/includes.isa:
need bigint.hh for Twin64_t
src/arch/sparc/isa/operands.isa:
add a twin 64 int type
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
add support for twinloads
add support for swap and conditional swap instructions
rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/mem/packet.cc:
src/mem/packet.hh:
Add support for atomic swap memory commands
src/mem/packet_access.hh:
Add endian conversion function for Twin64_t type
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
Add support for atomic swap memory commands
Rename sc code to extradata
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extra : convert_revision : 69d908512fb34a4e28b29a6e58b807fb1a6b1656
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--HG--
extra : convert_revision : 5f2c7d46c96fa061bbfb66edf188d405ca600020
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fix unaligned accesses in mmaped disk device
src/arch/sparc/isa/decoder.isa:
get (ld|st)fsr ops working right. In reality the fp enable check needs to go higher up in the emitted code
src/arch/sparc/isa/formats/basic.isa:
move the cexec into the aexec field
src/cpu/exetrace.cc:
copy the exception state from legion when we get it wrong. We aren't going to get it right without an fp emulation layer
src/dev/sparc/mm_disk.cc:
src/dev/sparc/mm_disk.hh:
fix unaligned accesses in the memory mapped disk device
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extra : convert_revision : aaa33096b08cf0563fe291d984a87493a117e528
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src/arch/sparc/isa/decoder.isa:
fix rdgsr fault check
src/arch/sparc/tlb.cc:
block asis are now supported
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extra : convert_revision : cf55d648d2c5184fab03b6fe057d0e33c1dfc393
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--HG--
extra : convert_revision : d0bb23c7922568586b640084ac719e809cc8422f
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src/arch/sparc/floatregfile.cc:
fix fp read/writing to registers... looking for suggestions on cleaner ways if anyone has them
src/arch/sparc/isa/decoder.isa:
fix some fp implementations
src/arch/sparc/isa/formats/basic.isa:
add new fp op class that 0 cexec in fsr and sets rounding mode for the up comming op
src/arch/sparc/isa/includes.isa:
include the appropriate header files for the rounding code
src/arch/sparc/miscregfile.cc:
print fsr out when it's read/written and the Sparc traceflgas in on
src/cpu/exetrace.cc:
fix printing of float registers
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extra : convert_revision : 49faab27f2e786a8455f9ca0f3f0132380c9d992
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into zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5
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extra : convert_revision : 62a0017a1147631513db7878f4e4d08fca776bc1
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extra : convert_revision : 6671c594b78d2e38449069157f39af96b81340f2
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src/SConscript:
strip doesn't take a src and dest in solaris
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extra : convert_revision : 57f95eda0e3232475a5b55753ace3f3f0fced8b3
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : 276b640c5c5a51e88e9bd630960ad462d9f0cb8d
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src/arch/sparc/floatregfile.cc:
Fix serialization for fpreg
src/arch/sparc/intregfile.cc:
fix serialization for intreg
src/arch/sparc/miscregfile.cc:
fix serialization from miscreg
src/arch/sparc/pagetable.cc:
fix serialization for page table
src/arch/sparc/regfile.cc:
need to serialize nnpc
src/arch/sparc/tlb.cc:
write serialization code for tlb
src/cpu/base.cc:
provide a way to find the thread number a context is
serialize the instruction counter
src/cpu/base.hh:
provide a way to find the thread number a context is
and given a thread number find a context pointer
src/cpu/cpuevent.hh:
provide method to get thread context from a cpu event for serialization
src/dev/sparc/t1000.cc:
src/dev/sparc/t1000.hh:
nothing to serialize in t1000
src/sim/serialize.cc:
src/sim/serialize.hh:
Make findObj() work (it hasn't since we did the python conversion stuff)
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extra : convert_revision : a95bc4e3c3354304171efbe3797556fdb146bea2
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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extra : convert_revision : 7b332ee4c737206511d26db391117eb1fe5ea290
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src/arch/sparc/isa/base.isa:
Added passesFpCondition function to help with fbfcc and fbpfcc instructions.
src/arch/sparc/isa/decoder.isa:
Added fbfcc and fbpfcc instructions, and cleaned up branch code slightly.
src/arch/sparc/isa/formats/branch.isa:
Minor cleanup.
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extra : convert_revision : 6586b46418f1f70bace41407f267fee30c657714
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way to do this.
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extra : convert_revision : 4f59ca8e6425db23f57a1f3f65a4874e483d0ecc
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extra : convert_revision : 06be0f8572e26c3c7e761b482248304ce1afa038
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setSingleStep
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extra : convert_revision : fde27a1faa6c03a24a4321a153dfa89a438f9a32
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extra : convert_revision : 84717cd3a8fa9fb85bd0693304e05ef475b05d07
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unimplemented floating point ops.
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extra : convert_revision : 356fec86c35560b20ea8eee80844602bbcec145f
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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extra : convert_revision : 0e4a54c21f32fec13deaf00b5d61c258007f172b
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--HG--
extra : convert_revision : 36137ee025dc5c79665b041b43bd89505715ca70
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right with respect to quite NaNs, but hopefully we don't need to worry about the distinction.
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extra : convert_revision : 67b6583a20530b7a393aa04d0b71031d3c72ecdd
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--HG--
extra : convert_revision : d2c538e7f469bd12a80eb8585c78d5325d6e6141
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : 7b8b791815d1fb51cc7ad085307a640b2ee51642
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--HG--
extra : convert_revision : 4665ac7760c9b78a1d7699ceeb541b694211a947
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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extra : convert_revision : 7bea2cb13e2de527134d98d4ee21a55dc4a7d1ad
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : e302dc4d7a20646bb0ea363127b2658a6d6e810c
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return correct traps for ua2005 fpops that aren't implemented in hw
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extra : convert_revision : 998fd43f77c5de7078bac1c6caab296b18c9366d
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make fp writes also chatty with the Sparc traceflag
src/arch/sparc/floatregfile.cc:
make fp writes also chatty with the Sparc traceflag
src/cpu/exetrace.cc:
fix comparing fp registers between legion and m5
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extra : convert_revision : f3703afae56249f137451262bc1b6919d465e714
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into zower.eecs.umich.edu:/eecshome/m5/newmem
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/system.cc:
Hand Merge
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extra : convert_revision : d5e0c97caebb616493e2f642e915969d7028109c
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--HG--
extra : convert_revision : a79f5ee225208338594e7c4ecf0a71fef941918c
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possible now becauase Ctrl_Base_DepTag gets added into control register numbers.
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extra : convert_revision : d6de3be277127547cd942769cd34a54a4ec8db32
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : 53ee81b099930d4d827db99e2d944ffb8645c706
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some fixes to fp instructions to use the single precision registers
if this is an fp op emit fp check code
add fpregs to m5legion struct
src/arch/sparc/floatregfile.cc:
Make Sparc traceflag even more chatty
src/arch/sparc/isa/base.isa:
add code to check if the fpu is enabled
src/arch/sparc/isa/decoder.isa:
some fixes to fp instructions to use the single precision registers
fix smul again
fix subc/subcc/subccc condition code setting
src/arch/sparc/isa/formats/basic.isa:
src/arch/sparc/isa/formats/mem/util.isa:
if this is an fp op emit fp check code
src/cpu/exetrace.cc:
check fp regs as well as int regs
src/cpu/m5legion_interface.h:
add fpregs to m5legion struct
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extra : convert_revision : e7d26d10fb8ce88f96e3a51f84b48c3b3ad2f232
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into zeep.pool:/z/saidi/work/m5.suncc
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extra : convert_revision : 1706f6218abec7eb575dcff3ad4aef83894f64ab
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into zeep.pool:/z/saidi/work/m5.suncc
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extra : convert_revision : 20f61a524a3b53fc0afcf53a24b5a1fe1d96f579
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pretty close to compiling w/ suns compiler
briefly:
add dummy return after panic()/fatal()
split out flags by compiler vendor
include cstring and cmath where appropriate
use std namespace for string ops
SConstruct:
Add code to detect compiler and choose cflags based on detected compiler
Fix zlib check to work with suncc
src/SConscript:
split out flags by compiler vendor
src/arch/sparc/isa/decoder.isa:
use correct namespace for sqrt
src/arch/sparc/isa/formats/basic.isa:
add dummy return around panic
src/arch/sparc/isa/formats/integerop.isa:
use correct namespace for stringops
src/arch/sparc/isa/includes.isa:
include cstring and cmath where appropriate
src/arch/sparc/isa_traits.hh:
remove dangling comma
src/arch/sparc/system.cc:
dummy return to make sun cc front end happy
src/arch/sparc/tlb.cc:
src/base/compression/lzss_compression.cc:
use std namespace for string ops
src/arch/sparc/utility.hh:
no reason to say something is unsigned unsigned int
src/base/compression/null_compression.hh:
dummy returns to for suncc front end
src/base/cprintf.hh:
use standard variadic argument syntax instead of gnuc specefic renaming
src/base/hashmap.hh:
don't need to define hash for suncc
src/base/hostinfo.cc:
need stdio.h for sprintf
src/base/loader/object_file.cc:
munmap is in std namespace not null
src/base/misc.hh:
use M5 generic noreturn macros
use standard variadic macro __VA_ARGS__
src/base/pollevent.cc:
we need file.h for file flags
src/base/random.cc:
mess with include files to make suncc happy
src/base/remote_gdb.cc:
malloc memory for function instead of having a non-constant in an array size
src/base/statistics.hh:
use std namespace for floor
src/base/stats/text.cc:
include math.h for rint (cmath won't work)
src/base/time.cc:
use suncc version of ctime_r
src/base/time.hh:
change macro to work with both gcc and suncc
src/base/timebuf.hh:
include cstring from memset and use std::
src/base/trace.hh:
change variadic macros to be normal format
src/cpu/SConscript:
add dummy returns where appropriate
src/cpu/activity.cc:
include cstring for memset
src/cpu/exetrace.hh:
include cstring fro memcpy
src/cpu/simple/base.hh:
add dummy return for panic
src/dev/baddev.cc:
src/dev/pciconfigall.cc:
src/dev/platform.cc:
src/dev/sparc/t1000.cc:
add dummy return where appropriate
src/dev/ide_atareg.h:
make define work for both gnuc and suncc
src/dev/io_device.hh:
add dummy returns where approirate
src/dev/pcidev.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.hh:
src/mem/dram.cc:
src/mem/packet.cc:
src/mem/port.cc:
include cstring for string ops
src/dev/sparc/mm_disk.cc:
add dummy return where appropriate
include cstring for string ops
src/mem/cache/miss/blocking_buffer.hh:
src/mem/port.hh:
Add dummy return where appropriate
src/mem/cache/tags/iic.cc:
cast hastSets to double for log() call
src/mem/physical.cc:
cast pmemAddr to char* for munmap
src/sim/byteswap.hh:
make define work for suncc and gnuc
--HG--
extra : convert_revision : ef8a1f1064e43b6c39838a85c01aee4f795497bd
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not just MaxGL.
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extra : convert_revision : 6fd090f112611db1e72a1f129dff03687d52930a
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into zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5
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extra : convert_revision : 1b854ec7caa33d3009383754206b643494c4c42d
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--HG--
extra : convert_revision : 58e960e5019f944c7ec5606e4b8c93ce42330719
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Only allow writing/reading of 32 bits of Y
Only allow writing/reading 32 bits of pc when pstate.am
Put any loaded data on the first half of a micro-op in uReg0 so it can't
overwrite the register we are using for address calculation
only erase a entry from the lookup table if it's valid
Put in a temporary check to make sure that lookup table and tlb array stay in sync
if we are interrupted in the middle of a mico-op, reset the micropc/nexpc
so we start on the first part of it when we come back
src/arch/sparc/isa/decoder.isa:
fix smul and sdiv to sign extend, and handle overflow/underflow corretly
Only allow writing/reading of 32 bits of Y
Only allow writing/reading 32 bits of pc when pstate.am
Put any loaded data on the first half of a micro-op in uReg0 so it can't
overwrite the register we are using for address calculation
src/arch/sparc/isa/formats/mem/blockmem.isa:
Put any loaded data on the first half of a micro-op in uReg0 so it can't
overwrite the register we are using for address calculation
src/arch/sparc/isa/includes.isa:
Use limits for 32bit underflow/overflow detection
src/arch/sparc/tlb.cc:
only erase a entry from the lookup table if it's valid
Put in a temporary check to make sure that lookup table and tlb array stay in sync
src/arch/sparc/tlb_map.hh:
add a print function to dump the tlb lookup table
src/cpu/simple/base.cc:
if we are interrupted in the middle of a mico-op, reset the micropc/nexpc
so we start on the first part of it when we come back
--HG--
extra : convert_revision : 50a23837fd888393a5c2aa35cbd1abeebb7f55d4
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into zower.eecs.umich.edu:/eecshome/m5/newmem
--HG--
extra : convert_revision : 2d7ae62a59b91d735bbac093f8a4ab542ea75eee
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check writability of tlb cache entry before using
update tagaccess in places I forgot to
move the tlb privileged test up since it is higher priority
src/arch/sparc/faults.cc:
save only 32 bits of PC/NPC if Pstate.am is set
src/arch/sparc/isa/decoder.isa:
return only 32 bits of PC/NPC if Pstate.am is set
increment cleanwin correctly
src/arch/sparc/tlb.cc:
check writability of cache entry
update tagaccess in a few more places
move the privileged test up since it is higher priority
src/cpu/exetrace.cc:
mask off upper bits of pc if pstate.am is set before comparing to legion
--HG--
extra : convert_revision : 02a51c141ee3f9a2600c28eac018ea7216f3655c
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into ewok.(none):/home/gblack/m5/newmemo3
src/sim/byteswap.hh:
Hand Merge
--HG--
extra : convert_revision : 640d33ad0c416934e8a5107768e7f1dce6709ca8
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