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2010-08-23Loader: Make the load address mask be a parameter of the system rather than ↵Ali Saidi
a constant. This allows one two different OS requirements for the same ISA to be handled. Some OSes are compiled for a virtual address and need to be loaded into physical memory that starts at address 0, while other bare metal tools generate images that start at address 0.
2010-08-22SPARC: Fix some style issues in utility.hh.Gabe Black
2010-08-17sim: revamp unserialization procedureSteve Reinhardt
Replace direct call to unserialize() on each SimObject with a pair of calls for better control over initialization in both ckpt and non-ckpt cases. If restoring from a checkpoint, loadState(ckpt) is called on each SimObject. The default implementation simply calls unserialize() if there is a corresponding checkpoint section, so we get backward compatibility for existing objects. However, objects can override loadState() to get other behaviors, e.g., doing other programmed initializations after unserialize(), or complaining if no checkpoint section is found. (Note that the default warning for a missing checkpoint section is now gone.) If not restoring from a checkpoint, we call the new initState() method on each SimObject instead. This provides a hook for state initializations that are only required when *not* restoring from a checkpoint. Given this new framework, do some cleanup of LiveProcess subclasses and X86System, which were (in some cases) emulating initState() behavior in startup via a local flag or (in other cases) erroneously doing initializations in startup() that clobbered state loaded earlier by unserialize().
2010-08-13CPU: Tidy up endianness handling for mmapped "IPR"s.Gabe Black
2010-06-03More minor gdb-related cleanup.Steve Reinhardt
Found several more stale includes and forward decls.
2010-05-14SPARC: Implement the version of movcc that uses the fp condition codes.Gabe Black
2010-02-12O3PCU: Split loads and stores that cross cache line boundaries.Timothy M. Jones
When each load or store is sent to the LSQ, we check whether it will cross a cache line boundary and, if so, split it in two. This creates two TLB translations and two memory requests. Care has to be taken if the first packet of a split load is sent but the second blocks the cache. Similarly, for a store, if the first packet cannot be sent, we must store the second one somewhere to retry later. This modifies the LSQSenderState class to record both packets in a split load or store. Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA to indicate whether unaligned memory accesses are allowed. This is used throughout the changed code so that compiler can optimise away code dealing with split requests for ISAs that don't need them.
2009-10-30Syscalls: Make system calls access arguments like a stack, not an array.Gabe Black
When accessing arguments for a syscall, the position of an argument depends on the policies of the ISA, how much space preceding arguments took up, and the "alignment" of the index for this particular argument into the number of possible storate locations. This change adjusts getSyscallArg to take its index parameter by reference instead of value and to adjust it to point to the possible location of the next argument on the stack, basically just after the current one. This way, the rules for the new argument can be applied locally without knowing about other arguments since those have already been taken into account implicitly. All system calls have also been changed to reflect the new interface. In a number of cases this made the implementation clearer since it encourages arguments to be collected in one place in order and then used as necessary later, as opposed to scattering them throughout the function or using them in place in long expressions. It also discourages using getSyscallArg over and over to retrieve the same value when a temporary would do the job.
2009-09-15Syscalls: Implement sysinfo() syscall.Vince Weaver
2009-09-15SPARC: Make resTemp in udivcc wide enough to hold all the bits we need.Vince Weaver
2009-08-01Clean up some inconsistencies with Request flags.Steve Reinhardt
2009-07-25SPARC: Fix a minor compile bug in native trace on gcc > 4.1.Gabe Black
2009-07-19CPU: Separate out native trace into ISA (in)dependent code and SimObjects.Gabe Black
--HG-- rename : src/cpu/nativetrace.cc => src/arch/sparc/nativetrace.cc rename : src/cpu/nativetrace.hh => src/arch/sparc/nativetrace.hh rename : src/cpu/NativeTrace.py => src/arch/x86/X86NativeTrace.py
2009-07-10SPARC: Set up a lookup table for integer register flattening.Gabe Black
Using a look up table changed the run time of the SPARC_FS solaris boot regression from: real 14m45.951s user 13m57.528s sys 0m3.452s to: real 12m19.777s user 12m2.685s sys 0m2.420s
2009-07-09SPARC: Fold the MiscRegFile all the way into the ISA object.Gabe Black
2009-07-08Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.Gabe Black
2009-07-08Registers: Add a registers.hh file as an ISA switched header.Gabe Black
This file is for register indices, Num* constants, and register types. copyRegs and copyMiscRegs were moved to utility.hh and utility.cc. --HG-- rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh
2009-07-08Registers: Eliminate the ISA defined RegFile class.Gabe Black
2009-07-08Registers: Move the PCs out of the ISAs and into the CPUs.Gabe Black
2009-07-08SPARC: Phase out SPARC's intregfile.hh.Gabe Black
2009-07-08Registers: Eliminate the ISA defined integer register file.Gabe Black
2009-07-08Registers: Eliminate the ISA defined floating point register file.Gabe Black
2009-07-08Registers: Get rid of the float register width parameter.Gabe Black
2009-07-08Registers: Add an ISA object which replaces the MiscRegFile.Gabe Black
This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
2009-07-05SPARC: Fix the parenthesis in inUserMode.Gabe Black
2009-05-17includes: sort includes againNathan Binkert
2009-05-17includes: use base/types.hh not inttypes.h or stdint.hNathan Binkert
2009-05-17types: Move stuff for global types into src/base/types.hhNathan Binkert
--HG-- rename : src/sim/host.hh => src/base/types.hh
2009-04-24SPARC: Tighten up the clone system call and SPARCs copyRegs.Gabe Black
2009-04-21syscall: Resolve conflicts between m5threads and Gabe's recent SE changes.Steve Reinhardt
2009-04-21Commit m5threads package.Daniel Sanchez
This patch adds limited multithreading support in syscall-emulation mode, by using the clone system call. The clone system call works for Alpha, SPARC and x86, and multithreaded applications run correctly in Alpha and SPARC.
2009-04-19SE mode: Make keeping track of the number of syscalls less hacky.Gabe Black
2009-04-15Get rid of the Unallocated thread context state.Steve Reinhardt
Basically merge it in with Halted. Also had to get rid of a few other functions that called ThreadContext::deallocate(), including: - InOrderCPU's setThreadRescheduleCondition. - ThreadContext::exit(). This function was there to avoid terminating simulation when one thread out of a multi-thread workload exits, but we need to find a better (non-cpu-centric) way.
2009-04-08tlb: More fixing of unified TLBNathan Binkert
2009-04-08tlb: Don't separate the TLB classes into an instruction TLB and a data TLBGabe Black
2009-02-28Fix Num_Syscall_Descs check bug in non-x86 ISAs.Steve Reinhardt
(See cset d35d2b28df38 for x86 fix.)
2009-02-27Processes: Make getting and setting system call arguments part of a process ↵Gabe Black
object.
2009-02-25ISA: Get rid of the get*RegName functions.Gabe Black
2009-02-25SPARC: Get rid of the state keeping track of register frames.Gabe Black
2009-02-25ISA: Set up common trace flags for tracing registers.Gabe Black
2009-02-25ISA: Get rid of FlattenIntIndex function.Gabe Black
2009-02-25SPARC: Get rid of flattenIndex in the int register file.Gabe Black
2009-02-25ISA: Use the "Stack" traceflag for DPRINTFs about the initial stack frame.Gabe Black
2009-02-25SPARC: Get rid of the setGlobals function.Gabe Black
2009-02-25SPARC: Get rid of the setCWP function.Gabe Black
2009-02-25SPARC: Add a traceflag for register windows.Gabe Black
2009-02-25CPU: Implement translateTiming which defers to translateAtomic, and convert ↵Gabe Black
the timing simple CPU to use it.
2009-02-25SPARC: Adjust a few instructions to not write registers in initiateAcc.Gabe Black
2009-02-25ISA: Replace the translate functions in the TLBs with translateAtomic.Gabe Black
2009-02-16sycalls: implement mremap() and add DATA flag for getrlimit(). mremap has ↵Lisa Hsu
been tested on Alpha, compiles for the rest but not tested. I don't see why it wouldn't work though.