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2007-08-26Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.Gabe Black
--HG-- extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
2007-08-26SPARC: Make sure unaligned access are caught on cached translations as well.Gabe Black
--HG-- extra : convert_revision : 5c1f3f585817a19a771164f809dfc2fdc1ab3fb2
2007-08-13SPARC: Make nops have the IsNop flag set.Gabe Black
In O3, a nop is used to carry faults down the pipeline that didn't originate from an instruction. If the instruction doesn't do anything, that is just returns NoFault, but doesn't have IsNop set, the NoFault will overwrite the fault that's being sent down and nothing will happen. --HG-- extra : convert_revision : 54d99002b550ca0e1cf14603f588dc1038e3e535
2007-08-13SPARC: Move tlb state into the tlb.Gabe Black
Each "strand" may need to have a private copy of this state, but I couldn't find anywhere in the spec that said that after looking briefly. This prevents writes to the thread context in o3 which was causing the pipeline to be flushed and stopping any forward progress. The other ASI accessible state will probably need to be accessed differently if/when we get O3 full system up and running. --HG-- extra : convert_revision : fa7fba812d7f76564ef4a23818e60f536710d557
2007-08-13SPARC: Make the spill and fill handlers use the correct ASI, and let ↵Gabe Black
No_Fault ASI accesses work. --HG-- extra : convert_revision : 3321bb91da02c1bec27fa34d0ba945cc976b6491
2007-08-01Merge with head.Gabe Black
--HG-- extra : convert_revision : 444901221e9a0b991213fbcd555f2f5cca67e91b
2007-08-01Merge Gabe and my changes to arch/mips/utility.hhAli Saidi
--HG-- extra : convert_revision : d5a9d74ee6edf71524ba5c03fb7f054cf9722213
2007-08-01Arguments: Get rid of duplicate code for the Arguments class in each ↵Ali Saidi
architecture. Move the argument files to src/sim and add a utility.cc file with a function getArguments() that returns the given argument in the architecture specific fashion. getArguments() was getArg() is the architecture specific Argument class and has had all magic numbers replaced with meaningful constants. Also add a function to the Argument class for testing if an argument is NULL. --HG-- rename : src/arch/alpha/arguments.cc => src/sim/arguments.cc rename : src/arch/alpha/arguments.hh => src/sim/arguments.hh extra : convert_revision : 8b93667bafaa03b52aadb64d669adfe835266b8e
2007-07-31Add a flag to indicate an instruction triggers a syscall in SE mode.Gabe Black
--HG-- extra : convert_revision : 1d0b3afdd8254f5b2fb4bbff1fa4a0536f78bb06
2007-07-29Merge Gabe's changes from head.Steve Reinhardt
--HG-- extra : convert_revision : d00b7b09c7f19bc0e37b385ef7c124f69c0e917f
2007-07-29X86: Initial stack frame fixes and constant shuffling.Gabe Black
The initial stack frame for x86 is now substantially more correct. The fixes made here can be back ported to SPARC and possible the other ISAs as well. The auxiliary vector types were moved to the LiveProcess base class because they are independent of ISA. Some of the types may only apply to Linux, though, so they may have to be moved. --HG-- extra : convert_revision : 89ace35fcc8eb9586d2fee8eeccbc3686499ef24
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
--HG-- extra : convert_revision : e06a950964286604274fba81dcca362d75847233
2007-07-26X86: Fix argument register indexing.Gabe Black
Code was assuming that all argument registers followed in order from ArgumentReg0. There is now an ArgumentReg array which is indexed to find the right index. There is a constant, NumArgumentRegs, which can be used to protect against using an invalid ArgumentReg. --HG-- extra : convert_revision : f448a3ca4d6adc3fc3323562870f70eec05a8a1f
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. --HG-- extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
2007-07-22Merge more changes in from head.Steve Reinhardt
--HG-- extra : convert_revision : 8f170f2754eccdb424a35b5b077225abcf6eee72
2007-07-18Make name, isMachineCheckFault, and isAlignmentFault const.Gabe Black
--HG-- extra : convert_revision : a27e0cbdfcb2a5fdc5979686f887cec7d106542b
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt
now encoded in cmd field. --HG-- extra : convert_revision : d67819b7e3ee4b9a5bf08541104de0a89485e90b
2007-06-21Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-micro src/cpu/o3/fetch_impl.hh: hand merge --HG-- extra : convert_revision : 3f71f3ac2035eec8b6f7bceb6906edb4dd09c045
2007-06-19Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into doughnut.hpl.hp.com:/home/gblack/newmem-o3-micro src/cpu/base_dyn_inst_impl.hh: src/cpu/o3/fetch_impl.hh: Hand merge --HG-- extra : convert_revision : 0c0692033ac30133672d8dfe1f1a27e9d9e95a3d
2007-06-19Make branches work by repopulating the predecoder every time through. This ↵Gabe Black
is probably fine as far as the predecoder goes, but the simple cpu might want to not refetch something it already has. That reintroduces the self modifying code problem though. --HG-- extra : convert_revision : 802197e65f8dc1ad657c6b346091e03cb563b0c0
2007-06-13Seperate the pc-pc and the pc of the incoming bytes, and get rid of the ↵Gabe Black
"moreBytes" which just takes a MachInst. src/arch/x86/predecoder.cc: Seperate the pc-pc and the pc of the incoming bytes, and get rid of the "moreBytes" which just takes a MachInst. Also make the "opSize" field describe the number of bytes and not the log of the number of bytes. --HG-- extra : convert_revision : 3a5ec7053ec69c5cba738a475d8b7fd9e6e6ccc0
2007-06-12Make microOp vs microop and macroOp vs macroop capitilization consistent.Gabe Black
src/arch/x86/isa/macroop.isa: Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code. src/arch/x86/isa/microops/base.isa: Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation. --HG-- extra : convert_revision : 6f4bacfa334c42732c845f9a7f211cbefc73f96f
2007-05-31Assign traceData to be NULL at BaseSimpleCPU constructor.Vincentius Robby
Initialize a temporary variable for thread->readPC() at setupFetchRequest() to reduce function calls. exec tracing isn't needed for m5.fast binaries Moved MISCREG_GL, MISCREG_CWP, and MISCREG_TLB_DATA out of switch statement and use if blocks instead. src/arch/sparc/miscregfile.cc: Moved MISCREG_GL, MISCREG_CWP, and MISCREG_TLB_DATA out of switch statement and use if blocks instead. src/cpu/simple/base.cc: Assign traceData to be NULL at BaseSimpleCPU constructor. Initialize a temporary variable for thread->readPC() at setupFetchRequest() to reduce function calls. exec tracing isn't needed for m5.fast binaries --HG-- extra : convert_revision : 5dc92fff05c9bde994f1e0f1bb40e11c44eb72c6
2007-05-27Move SimObject python files alongside the C++ and fixNathan Binkert
the SConscript files so that only the objects that are actually available in a given build are compiled in. Remove a bunch of files that aren't used anymore. --HG-- rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py rename : src/python/m5/objects/Device.py => src/dev/Device.py rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py rename : src/python/m5/objects/Ide.py => src/dev/Ide.py rename : src/python/m5/objects/Pci.py => src/dev/Pci.py rename : src/python/m5/objects/Platform.py => src/dev/Platform.py rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py rename : src/python/m5/objects/Uart.py => src/dev/Uart.py rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py rename : src/python/m5/objects/Bus.py => src/mem/Bus.py rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py rename : src/python/m5/objects/Process.py => src/sim/Process.py rename : src/python/m5/objects/Root.py => src/sim/Root.py rename : src/python/m5/objects/System.py => src/sim/System.py extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
2007-05-09Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into doughnut.mwconnections.com:/home/gblack/newmem-o3-micro --HG-- extra : convert_revision : 56c2205cdbb9af64c30b381a80b4d14c97841da7
2007-05-09Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into doughnut.mwconnections.com:/home/gblack/newmem-o3-micro --HG-- extra : convert_revision : 545b9e98eb1895f4b9e782224fb6615c71ed6323
2007-05-09fix the translating ports so it can add a page on a faultAli Saidi
--HG-- extra : convert_revision : 56f6f2cbf4e92b7f2dd8c9453831fab86d83ef80
2007-05-08Add a hack to truncate addresses to 32 bits in SE. Paging should be changed ↵Gabe Black
to use the architecture's TLB, at which point this can be removed. --HG-- extra : convert_revision : 54f3c18e5aead727d0ac244ed00fd97d3ca8ad75
2007-04-27gcc 4.1 claims that mem_data might be used uninitialized,Nathan Binkert
though I don't believe that's true. Placate it anyway. --HG-- extra : convert_revision : dcd9427af14f0e7a33510054bee4ecbe73e050be
2007-04-23Merge zizzer.eecs.umich.edu:/n/wexford/x/gblack/m5/newmem-o3-specGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-micro --HG-- extra : convert_revision : 757e1d79033e6f8e0aaaf5ecaf14077d416cff8e
2007-04-23Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemGabe Black
into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-o3-spec --HG-- extra : convert_revision : 12f10c174f0eca1ddf74b672414fbe78251f686b
2007-04-22Make the GSR into a renamed control register. It should be split into a ↵Gabe Black
renamed part and a control part for the different bitfields, but the renamed part is all that's actually used. --HG-- extra : convert_revision : ffeb4f874bd4430255064f6e8bcb135309932ff8
2007-04-21create base/fenv.c to standerdize fenv across platforms. It's a c file and ↵Ali Saidi
not a cpp file because c99 (which defines fenv) doesn't necessarily extend to c++ and it is a problem with solaris. If really desired this could wrap the ieeefp interface found in bsd* as well, but I see no need at the moment. src/arch/alpha/isa/fp.isa: src/arch/sparc/isa/formats/basic.isa: use m5_fesetround()/m5_fegetround() istead of fenv interface directly src/arch/sparc/isa/includes.isa: use base/fenv instead of fenv directly src/base/SConscript: add fenv to sconscript src/base/fenv.hh: src/base/random.cc: m5 implementation to standerdize fenv across platforms. --HG-- extra : convert_revision : 38d2629affd964dcd1a5ab0db4ac3cb21438e72c
2007-04-14Make register indexes larger so they can actually hold all the legal values. ↵Gabe Black
Oops! --HG-- extra : convert_revision : 7689b2e1f7468e4acb8be0f242f74002c79e7960
2007-04-14Make the fsr a serializing register. Other control registers probably need ↵Gabe Black
this as well. --HG-- extra : convert_revision : edd3f9a83cc2722b6e0eff0eff4a8e034b0f6ec6
2007-04-11Make trying to execute macroops fail with a better error message.Gabe Black
--HG-- extra : convert_revision : e81c0337d6db4b5a33381ed19686750bbb9d9178
2007-04-11Create a filter and a union to translate the SPARC instruction ↵Gabe Black
implementations from using doubles to using concatenated singles. --HG-- extra : convert_revision : 609ba35bbb13cbd1998e93957cb051461442d1f9
2007-04-08Get the "hard" SPARC instructions working in o3. I don't like that the ↵Gabe Black
IsStoreConditional flag needs to be set for them because they aren't store conditional instructions, and I should fix the format code which is not handling the opt_flags correctly. --HG-- extra : convert_revision : cfd32808592832d7b6fbdaace5ae7b17c8a246e9
2007-03-29get rid of CWP bounds warning...Ali Saidi
--HG-- extra : convert_revision : 74df09341c091c2d6ca9b46c6a3521f22b48acf4
2007-03-23Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zower.eecs.umich.edu:/home/gblack/m5/newmem-o3-spec --HG-- extra : convert_revision : 6b1c8025d29f3e8f90906805dd51a5d523d56004
2007-03-21Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace --HG-- extra : convert_revision : 41214c71e7fa11d47395975a141793337d020463
2007-03-20Ignore "time" and "times" syscalls.Gabe Black
--HG-- extra : convert_revision : 3ff55e35877c0fd74823ce5e52ed16c38da92068
2007-03-18Compile fixes for SPARC_FS.Gabe Black
src/arch/alpha/predecoder.hh: src/arch/sparc/predecoder.hh: Put in a missing include src/cpu/exetrace.cc: Convert the legion lockstep stuff from makeExtMI to the predecoder object. --HG-- extra : convert_revision : 91bad4466f8db1447fff8608fa46a5f236dc3a89
2007-03-17The syntax used for twin stores was confusing the parser so it's now broken ↵Gabe Black
down farther. --HG-- extra : convert_revision : d36bef2d15bc013b3c6199901f57855dfb9dab76
2007-03-16Make the SPARC branch instructions use ExtMachInsts in their constructors. ↵Gabe Black
This isn't necessary since they don't use the extended fields, but it's more consistent and more correct. --HG-- extra : convert_revision : afd4f408122ad5e497012eb9744d6bce66a1de37
2007-03-15Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 src/arch/mips/utility.hh: src/arch/x86/SConscript: Hand merge --HG-- extra : convert_revision : 0ba457aab52bf6ffc9191fd1fe1006ca7704b5b0
2007-03-15Make the predecoder an object with it's own switched header file. Start ↵Gabe Black
adding predecoding functionality to x86. src/arch/SConscript: src/arch/alpha/utility.hh: src/arch/mips/utility.hh: src/arch/sparc/utility.hh: src/cpu/base.hh: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/static_inst.hh: src/arch/alpha/predecoder.hh: src/arch/mips/predecoder.hh: src/arch/sparc/predecoder.hh: Make the predecoder an object with it's own switched header file. --HG-- extra : convert_revision : 77206e29089130e86b97164c30022a062699ba86
2007-03-13Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace --HG-- extra : convert_revision : 61eca737296a5ce839d3b97f047b4fda062cb899
2007-03-13Replaced makeExtMI with predecode.Gabe Black
Removed the getOpcode function from StaticInst which only made sense for Alpha. Started implementing the x86 predecoder. --HG-- extra : convert_revision : a13ea257c8943ef25e9bc573024a99abacf4a70d
2007-03-13fix interrupting during a quisce on sparcAli Saidi
src/arch/sparc/ua2005.cc: fix interrupting when quisced. Since sticks correspond to instructions when not quisced we need to check if were suspended and interrupt at the guess time src/base/traceflags.py: add trace flag for Iob src/cpu/simple/base.cc: Use Quisce instead of IPI trace flag src/dev/sparc/iob.cc: add some Dprintfs --HG-- extra : convert_revision : 72e18fcc750ad1e4b2bb67b19b354eaffc6af6d5
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-05 22:35:11 +0000