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2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
The ISA class on stores the contents of ID registers on many architectures. In order to make reset values of such registers configurable, we make the class inherit from SimObject, which allows us to use the normal generated parameter headers. This patch introduces a Python helper method, BaseCPU.createThreads(), which creates a set of ISAs for each of the threads in an SMT system. Although it is currently only needed when creating multi-threaded CPUs, it should always be called before instantiating the system as this is an obvious place to configure ID registers identifying a thread/CPU.
2012-06-05ISA: Back-out NoopMachInst as a StaticInstPtr change.Ali Saidi
2012-06-04ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.Gabe Black
This eliminates a use of the ExtMachInst type outside of the ISAs.
2012-05-26CPU: Merge the predecoder and decoder.Gabe Black
These classes are always used together, and merging them will give the ISAs more flexibility in how they cache things and manage the process. --HG-- rename : src/arch/x86/predecoder_tables.cc => src/arch/x86/decoder_tables.cc
2012-05-25ISA: Make the decode function part of the ISA's decoder.Gabe Black
2011-10-30X86: Build the same files in SE and FS.Gabe Black
2011-10-13X86: Build vtophys in SE mode.Gabe Black
2011-10-13X86: Turn on the page table walker in SE mode.Gabe Black
2011-10-09SE/FS: Build the Interrupt objects in SE mode.Gabe Black
2011-09-30X86: Remove FULL_SYSTEM from the x86 faults.Gabe Black
2011-06-02scons: rename TraceFlags to DebugFlagsNathan Binkert
2011-02-13X86: On a bad microopc, return a microop that returns a fault that panics.Gabe Black
This way a bad micropc will have to get all the way to commit before killing the simulation. This accounts for misspeculated branches.
2010-08-23X86: Make the x86 ExtMachInst serializable with (UN)SERIALIZE_SCALAR.Gabe Black
--HG-- rename : src/arch/x86/types.hh => src/arch/x86/types.cc
2010-05-23copyright: Change HP copyright on x86 code to be more friendlyNathan Binkert
2009-08-17X86: Create base classes for use with media/SIMD microops.Gabe Black
2009-07-19CPU: Separate out native trace into ISA (in)dependent code and SimObjects.Gabe Black
--HG-- rename : src/cpu/nativetrace.cc => src/arch/sparc/nativetrace.cc rename : src/cpu/nativetrace.hh => src/arch/sparc/nativetrace.hh rename : src/cpu/NativeTrace.py => src/arch/x86/X86NativeTrace.py
2009-07-09X86: Fold the MiscRegFile all the way into the ISA object.Gabe Black
2009-07-08Registers: Add a registers.hh file as an ISA switched header.Gabe Black
This file is for register indices, Num* constants, and register types. copyRegs and copyMiscRegs were moved to utility.hh and utility.cc. --HG-- rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh
2009-07-08Registers: Eliminate the ISA defined integer register file.Gabe Black
2009-07-08Registers: Eliminate the ISA defined floating point register file.Gabe Black
2009-07-08Registers: Add an ISA object which replaces the MiscRegFile.Gabe Black
This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
2009-02-25X86: Implement CLTS.Gabe Black
2009-02-25X86: Add a trace flag for tracing faults.Gabe Black
2009-02-25X86: Add a trace flag for the page table walker.Gabe Black
2009-01-19tracing: Add help strings for some of the trace flagsNathan Binkert
2009-01-13SCons: centralize the Dir() workaround for newer versions of scons.Nathan Binkert
Scons bug id: 2006 M5 Bug id: 308
2008-10-12X86: Implement entering an interrupt in microcode.Gabe Black
2008-10-12X86: Implement CPUID with a magical function instead of microcode.Gabe Black
2008-10-12X86: Add a LocalApic trace flag.Gabe Black
2008-10-12Turn Interrupts objects into SimObjects. Also, move local APIC state into ↵Gabe Black
x86's Interrupts object.
2008-10-10X86: Move the smbios objects into a folder for BIOS objects.Gabe Black
2008-06-12X86: Make the e820 table manually or automatically configurable from python.Gabe Black
2008-06-11SCons: Fix more SCons version issuesAli Saidi
2008-02-26X86: Implement the INVLPG instruction and the TIA microop.Gabe Black
--HG-- extra : convert_revision : 31db1ee082f6c3ca5443cba1eb335e408661ead2
2008-01-23X86: Put an SMBios/DMI table in memory.Gabe Black
This is basically just the header right now, but there's an untested mechanism in place to fill out the table and make sure everything is updated correctly. --HG-- extra : convert_revision : c1610c0dfa211b7e0d091a04133695d84f500a1c
2007-12-01X86: Move startup code to the system object to initialize a Linux system.Gabe Black
--HG-- extra : convert_revision : a4796c79f41aa8b8f38bf2f628bee8f1b3af64be
2007-12-01X86: Add a missing microcode file to the sconscript.Gabe Black
--HG-- extra : convert_revision : 6da8a67e07bada169abf7f10aded8a90d4e63eae
2007-11-12X86: Separate out the page table walker into it's own cc and hh.Gabe Black
--HG-- extra : convert_revision : cbc3af01ca3dc911a59224a574007c5c0bcf6042
2007-10-31Traceflags: Add SCons function to created a traceflag instead of having one ↵Ali Saidi
file with them all. --HG-- extra : convert_revision : 427f6bd8f050861ace3bc0d354a1afa5fc8319e6
2007-10-19X86: Impelement the HLT instruction and fix the "halt" microop.Gabe Black
--HG-- extra : convert_revision : 932e5bb5bf3644f8468dba92177fb87cc54b891a
2007-10-12X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions.Gabe Black
There are no priviledge checks, so these instructions will all work in all modes. --HG-- extra : convert_revision : ff893eb569313d8aecbfffb47bcbd1c2d65cd393
2007-10-07X86: Make initCPU and startupCPU do something basic.Gabe Black
--HG-- extra : convert_revision : 1a04f4402f4f31e4e5cd482c7983d853fe117df5
2007-10-07X86: Make an x86 system object.Gabe Black
--HG-- extra : convert_revision : 590a4c29cb9b943a2d8c3a97c5fdfbabb658ac45
2007-10-02X86: Start implementing the x86 tlb which will handle segmentation ↵Gabe Black
permission and limit checks and paging. --HG-- extra : convert_revision : 6072f7d9eecbaa066d39d6da7f0180ea4a2615af
2007-09-24X86: Get X86_FS to compile.Gabe Black
--HG-- extra : convert_revision : fb973bcf13648876d5691231845dd47a2be50f01
2007-09-19X86: Move the fp microops to their own file with their own base classes in ↵Gabe Black
C++ and python. --HG-- extra : convert_revision : 9cd223f2005adb36fea2bb56fa39793a58ec958c
2007-09-19X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.Gabe Black
--HG-- rename : src/arch/x86/isa/insts/sse/__init__.py => src/arch/x86/isa/insts/simd128/__init__.py extra : convert_revision : efb4405aebaa4a04f33572e7d078ceca45872d9c
2007-09-10X86: Make the isa parser run if any of the microcode files change.Gabe Black
--HG-- extra : convert_revision : 7f6d07de7e0d728a9333fb46c953dbe6cb04e600
2007-08-26Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.Gabe Black
--HG-- extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
2007-07-14Pull some hard coded base classes out of the isa description.Gabe Black
--HG-- rename : src/arch/x86/isa/base.isa => src/arch/x86/isa/outputblock.isa extra : convert_revision : 7954e7d5eea3b5966c9e273a08bcd169a39f380c
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