| Age | Commit message (Expand) | Author |
|---|
| 2013-08-07 | x86: add tlb checkpointing | Nilay Vaish |
| 2013-05-21 | x86: Squash outstanding walks when instructions are squashed. | Gedare Bloom |
| 2012-11-02 | sim: Include object header files in SWIG interfaces | Andreas Sandberg |
| 2012-02-13 | MEM: Introduce the master/slave port roles in the Python classes | Andreas Hansson |
| 2011-10-13 | X86: Turn on the page table walker in SE mode. | Gabe Black |
| 2010-05-23 | copyright: Change HP copyright on x86 code to be more friendly | Nathan Binkert |
| 2009-09-22 | python: Move more code into m5.util allow SCons to use that code. | Nathan Binkert |
| 2009-04-08 | tlb: Don't separate the TLB classes into an instruction TLB and a data TLB | Gabe Black |
| 2008-10-10 | TLB: Make all tlbs derive from a common base class in both python and C++. | Gabe Black |
| 2008-10-09 | SimObjects: Clean up handling of C++ namespaces. | Nathan Binkert |
| 2008-06-14 | Fix various SWIG warnings | Nathan Binkert |
| 2007-11-12 | X86: Separate out the page table walker into it's own cc and hh. | Gabe Black |
| 2007-11-12 | X86: Work on the page table walker, TLB, and related faults. | Gabe Black |
| 2007-11-12 | X86: Implement a page table walker. | Gabe Black |
| 2007-10-02 | X86: Start implementing the x86 tlb which will handle segmentation permission... | Gabe Black |
| 2007-08-26 | Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. | Gabe Black |
