gem5 - gem5

Age	Commit message (Collapse)	Author
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
	This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves. The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port. Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves.
2011-10-13	X86: Turn on the page table walker in SE mode.	Gabe Black

2010-05-23	copyright: Change HP copyright on x86 code to be more friendly	Nathan Binkert

2009-09-22	python: Move more code into m5.util allow SCons to use that code.	Nathan Binkert
	Get rid of misc.py and just stick misc things in __init__.py Move utility functions out of SCons files and into m5.util Move utility type stuff from m5/__init__.py to m5/util/__init__.py Remove buildEnv from m5 and allow access only from m5.defines Rename AddToPath to addToPath while we're moving it to m5.util Rename read_command to readCommand while we're moving it Rename compare_versions to compareVersions while we're moving it. --HG-- rename : src/python/m5/convert.py => src/python/m5/util/convert.py rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
2009-04-08	tlb: Don't separate the TLB classes into an instruction TLB and a data TLB	Gabe Black

2008-10-10	TLB: Make all tlbs derive from a common base class in both python and C++.	Gabe Black

2008-10-09	SimObjects: Clean up handling of C++ namespaces.	Nathan Binkert
	Make them easier to express by only having the cxx_type parameter which has the full namespace name, and drop the cxx_namespace thing. Add support for multiple levels of namespace.
2008-06-14	Fix various SWIG warnings	Nathan Binkert

2007-11-12	X86: Separate out the page table walker into it's own cc and hh.	Gabe Black
	--HG-- extra : convert_revision : cbc3af01ca3dc911a59224a574007c5c0bcf6042
2007-11-12	X86: Work on the page table walker, TLB, and related faults.	Gabe Black
	--HG-- extra : convert_revision : 9edde958b7e571c07072785f18f9109f73b8059f
2007-11-12	X86: Implement a page table walker.	Gabe Black
	--HG-- extra : convert_revision : 36bab5750100318faa9ba7178dc2e38590053aec
2007-10-02	X86: Start implementing the x86 tlb which will handle segmentation ↵	Gabe Black
	permission and limit checks and paging. --HG-- extra : convert_revision : 6072f7d9eecbaa066d39d6da7f0180ea4a2615af
2007-08-26	Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.	Gabe Black
	--HG-- extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1