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path: root/src/arch/x86/X86TLB.py
AgeCommit message (Expand)Author
2013-05-21x86: Squash outstanding walks when instructions are squashed.Gedare Bloom
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2011-10-13X86: Turn on the page table walker in SE mode.Gabe Black
2010-05-23copyright: Change HP copyright on x86 code to be more friendlyNathan Binkert
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
2009-04-08tlb: Don't separate the TLB classes into an instruction TLB and a data TLBGabe Black
2008-10-10TLB: Make all tlbs derive from a common base class in both python and C++.Gabe Black
2008-10-09SimObjects: Clean up handling of C++ namespaces.Nathan Binkert
2008-06-14Fix various SWIG warningsNathan Binkert
2007-11-12X86: Separate out the page table walker into it's own cc and hh.Gabe Black
2007-11-12X86: Work on the page table walker, TLB, and related faults.Gabe Black
2007-11-12X86: Implement a page table walker.Gabe Black
2007-10-02X86: Start implementing the x86 tlb which will handle segmentation permission...Gabe Black
2007-08-26Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.Gabe Black