Age | Commit message (Collapse) | Author |
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Same exception is raised whether division with zero is performed or the
quotient is greater than the maximum value that the provided space can hold.
Divide-by-Zero is the AMD terminology, while Divide-Error is Intel's.
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The TLB-related code is generally architecture dependent and should
live in the arch directory to signify that.
--HG--
rename : src/sim/BaseTLB.py => src/arch/generic/BaseTLB.py
rename : src/sim/tlb.cc => src/arch/generic/tlb.cc
rename : src/sim/tlb.hh => src/arch/generic/tlb.hh
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This patch optimises the passing of StaticInstPtr by avoiding copying
the reference-counting pointer. This avoids first incrementing and
then decrementing the reference-counting pointer.
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This patch allows a hardware virtualized CPU to discover which interrupt
to deliver to the guest.
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This patch cleans up a number of minor issues aiming to get closer to
compliance with the C++0x standard as interpreted by gcc and clang
(compile with std=c++0x and -pedantic-errors). In particular, the
patch cleans up enums where the last item was succeded by a comma,
namespaces closed by a curcly brace followed by a semi-colon, and the
use of the GNU-extension typeof (replaced by templated functions). It
does not address variable-length arrays, zero-size arrays, anonymous
structs, range expressions in switch statements, and the use of long
long. The generated CPU code also has a large number of issues that
remain to be fixed, mainly related to overflows in implicit constant
conversion (due to shifts).
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Even though this shouldn't ever be used, it might get called speculatively and
shouldn't panic.
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Also move the "Fault" reference counted pointer type into a separate file,
sim/fault.hh. It would be better to name this less similarly to sim/faults.hh
to reduce confusion, but fault.hh matches the name of the type. We could change
Fault to FaultPtr to match other pointer types, and then changing the name of
the file would make more sense.
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The fault object, if invoked, would then panic. This is a bit less direct, but
it means speculative execution won't panic the simulator.
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the fake TLB miss faults.
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accordingly.
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--HG--
extra : convert_revision : 9edde958b7e571c07072785f18f9109f73b8059f
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--HG--
extra : convert_revision : 7576f8cfaec9ddfb65e6ba7a6f64a5f453a42069
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permission and limit checks and paging.
--HG--
extra : convert_revision : 6072f7d9eecbaa066d39d6da7f0180ea4a2615af
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--HG--
extra : convert_revision : bc060a01b5415551b335ca68ccbf126333ae20b0
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The page table now stores actual page table entries. It is still a templated
class here, but this will be corrected in the near future.
--HG--
extra : convert_revision : 804dcc6320414c2b3ab76a74a15295bd24e1d13d
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--HG--
extra : convert_revision : eb71bc3edd92a544a5333786635fce550aaef233
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unimplemented instructions in their microcode. This is useful if certain variations of an instruction are implemented, but, for instance, it's memory based versions aren't.
--HG--
extra : convert_revision : 24e69c5a6a0af2d0cf67e858a051ae6624bb300f
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The page table fault should be moved into sim/faults.hh because it's a "fake" m5 fault for se mode and shouldn't vary between architectures.
--HG--
extra : convert_revision : cafe25befd64f83a424c1a09f5e62a16df5408ad
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--HG--
extra : convert_revision : 62583e5a5647913fb36e1aae265e8ac52a165829
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--HG--
extra : convert_revision : abfcf4005ec636b1e6c085515b63c1d8e69e3370
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--HG--
extra : convert_revision : 438eb74f14e6ea60bab5012110f3946c9213786e
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