gem5 - gem5

Age	Commit message (Collapse)	Author
2017-07-05	cpu: Simplify the rename interface and use RegId	Rekai Gonzalez-Alberquilla
	With the hierarchical RegId there are a lot of functions that are redundant now. The idea behind the simplification is that instead of having the regId, telling which kind of register read/write/rename/lookup/etc. and then the function panic_if'ing if the regId is not of the appropriate type, we provide an interface that decides what kind of register to read depending on the register type of the given regId. Change-Id: I7d52e9e21fc01205ae365d86921a4ceb67a57178 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2702
2017-07-05	arch, cpu: Architectural Register structural indexing	Nathanael Premillieu
	Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700
2016-02-06	x86: revamp cmpxchg8b/cmpxchg16b implementation	Alexandru Dutu
	The previous implementation did a pair of nested RMW operations, which isn't compatible with the way that locked RMW operations are implemented in the cache models. It was convenient though in that it didn't require any new micro-ops, and supported cmpxchg16b using 64-bit memory ops. It also worked in AtomicSimpleCPU where atomicity was guaranteed by the core and not by the memory system. It did not work with timing CPU models though. This new implementation defines new 'split' load and store micro-ops which allow a single memory operation to use a pair of registers as the source or destination, then uses a single ldsplit/stsplit RMW pair to implement cmpxchg. This patch requires support for 128-bit memory accesses in the ISA (added via a separate patch) to support cmpxchg16b.
2014-10-16	arch,x86,mem: Dynamically determine the ISA for Ruby store check	Andreas Hansson
	This patch makes the memory system ISA-agnostic by enabling the Ruby Sequencer to dynamically determine if it has to do a store check. To enable this check, the ISA is encoded as an enum, and the system is able to provide the ISA to the Sequencer at run time. --HG-- rename : src/arch/x86/insts/microldstop.hh => src/arch/x86/ldstflags.hh
2012-04-15	X86: Fix a tiny typo in the load/store microop constructor.	Gabe Black
	The parameter is _machInst, which is very similar to the member machInst. If machInst is used to pass the parameter to a lower level constructor, what really happens is that machInst is set to whatever it already happened to be, effectively leaving it uninitialized.
2011-07-02	ISA: Use readBytes/writeBytes for all instruction level memory operations.	Gabe Black

2010-09-13	Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.	Gabe Black
	Also move the "Fault" reference counted pointer type into a separate file, sim/fault.hh. It would be better to name this less similarly to sim/faults.hh to reduce confusion, but fault.hh matches the name of the type. We could change Fault to FaultPtr to match other pointer types, and then changing the name of the file would make more sense.
2010-08-23	X86: Consolidate extra microop flags into one parameter.	Gabe Black
	This single parameter replaces the collection of bools that set up various flavors of microops. A flag parameter also allows other flags to be set like the serialize before/after flags, etc., without having to change the constructor.
2010-05-23	copyright: Change HP copyright on x86 code to be more friendly	Nathan Binkert

2009-08-21	X86: fix some simple compile issues	Nathan Binkert
	static should not be used for constants that are not inside a class definition.
2009-07-16	X86: Take limitted advantage of the compilers type checking for microop ↵	Gabe Black
	operands.
2009-04-23	X86: Put the StoreCheck flag with the others, and don't collide with other ↵	Gabe Black
	flags.
2009-02-27	X86: Fix segment limit checks.	Gabe Black

2009-02-25	X86: Add a flag to force memory accesses to happen at CPL 0.	Gabe Black

2008-11-09	X86: Fix completeAcc get call.	Gabe Black

2007-08-26	X86: Remove x86 code that attempted to fix misaligned accesses.	Gabe Black
	--HG-- extra : convert_revision : 42f68010e6498aceb7ed25da278093e99150e4df
2007-08-04	X86: Make 64 bit unaligned accesses work as well as the other sizes.	Gabe Black
	There is a fundemental flaw in how unaligned accesses are supported, but this is still an improvement. --HG-- extra : convert_revision : 1c20b524ac24cd4a812c876b067495ee6a7ae29f
2007-07-30	X86: Make disassembly use the final register index. Add bits to indicate ↵	Gabe Black
	whether or not register indexes should be "folded". --HG-- extra : convert_revision : 4b46e71ca91e480f6e1662b7f37b75240d6598e9
2007-07-26	X86: Add functions to read and write to an exec context.	Gabe Black
	These functions take care of calling the thread contexts read and write functions with the right sized data type, and handle unaligned accesses. --HG-- extra : convert_revision : b4b59ab2b22559333035185946bae3eab316c879
2007-07-14	Pull some hard coded base classes out of the isa description.	Gabe Black
	--HG-- rename : src/arch/x86/isa/base.isa => src/arch/x86/isa/outputblock.isa extra : convert_revision : 7954e7d5eea3b5966c9e273a08bcd169a39f380c