Age | Commit message (Collapse) | Author |
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extra : convert_revision : d98b2d95448cab4e689d01ceedaa6ad46f9ffc09
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C++ and python.
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extra : convert_revision : 9cd223f2005adb36fea2bb56fa39793a58ec958c
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extra : convert_revision : 663021070a4bcc795bb44e1839b8bcec686a42f0
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Fixed the asz assembler symbol.
Adjusted the condion checks to have appropriate options.
Implemented the SCAS microcode.
Attached SCAS into the decoder.
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extra : convert_revision : 17bf9ddae6bc2069e43b076f8f83c4e54fb7966c
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whether or not register indexes should be "folded".
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extra : convert_revision : 4b46e71ca91e480f6e1662b7f37b75240d6598e9
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subtract.
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extra : convert_revision : d01bb791b000a2fdfc8600f8fb2f8aadd52b0b63
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This doesn't handle high byte register accesses. It also highlights the fact that address size isn't actually being calculated, and that the size a microop uses needs to be overridable from the microassembly.
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extra : convert_revision : d495ac4f5756dc55a5f71953ff6963b3c030e6cb
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Some microops can set the condition codes, and some of them can be predicated on them. Some of the codes aren't implemented because it was unclear from the AMD patent what they actually did. They are used with string instructions, but they use variables IP, DTF, and SSTF which don't appear to be documented.
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extra : convert_revision : 2236cccd07d0091762b50148975f301bb1d2da3f
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--HG--
rename : src/arch/x86/isa/base.isa => src/arch/x86/isa/outputblock.isa
extra : convert_revision : 7954e7d5eea3b5966c9e273a08bcd169a39f380c
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