gem5 - gem5

Age	Commit message (Collapse)	Author
2007-09-19	X86: Move the fp microops to their own file with their own base classes in ↵	Gabe Black
	C++ and python. --HG-- extra : convert_revision : 9cd223f2005adb36fea2bb56fa39793a58ec958c
2007-08-07	X86: Implemented and hooked in SCAS (scan string)	Gabe Black
	Fixed the asz assembler symbol. Adjusted the condion checks to have appropriate options. Implemented the SCAS microcode. Attached SCAS into the decoder. --HG-- extra : convert_revision : 17bf9ddae6bc2069e43b076f8f83c4e54fb7966c
2007-07-30	X86: Make disassembly use the final register index. Add bits to indicate ↵	Gabe Black
	whether or not register indexes should be "folded". --HG-- extra : convert_revision : 4b46e71ca91e480f6e1662b7f37b75240d6598e9
2007-07-20	Fixed width parameter and provided a parameter to flip the carry bit on ↵	Gabe Black
	subtract. --HG-- extra : convert_revision : d01bb791b000a2fdfc8600f8fb2f8aadd52b0b63
2007-07-17	Add in support for condition code flags.	Gabe Black
	Some microops can set the condition codes, and some of them can be predicated on them. Some of the codes aren't implemented because it was unclear from the AMD patent what they actually did. They are used with string instructions, but they use variables IP, DTF, and SSTF which don't appear to be documented. --HG-- extra : convert_revision : 2236cccd07d0091762b50148975f301bb1d2da3f
2007-07-14	Pull some hard coded base classes out of the isa description.	Gabe Black
	--HG-- rename : src/arch/x86/isa/base.isa => src/arch/x86/isa/outputblock.isa extra : convert_revision : 7954e7d5eea3b5966c9e273a08bcd169a39f380c