gem5 - gem5

Age	Commit message (Collapse)	Author
2017-07-05	cpu: Simplify the rename interface and use RegId	Rekai Gonzalez-Alberquilla
	With the hierarchical RegId there are a lot of functions that are redundant now. The idea behind the simplification is that instead of having the regId, telling which kind of register read/write/rename/lookup/etc. and then the function panic_if'ing if the regId is not of the appropriate type, we provide an interface that decides what kind of register to read depending on the register type of the given regId. Change-Id: I7d52e9e21fc01205ae365d86921a4ceb67a57178 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2702
2017-07-05	arch, cpu: Architectural Register structural indexing	Nathanael Premillieu
	Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700
2016-11-09	style: [patch 1/22] use /r/3648/ to reorganize includes	Brandon Potter

2016-02-06	style: fix missing spaces in control statements	Steve Reinhardt
	Result of running 'hg m5style --skip-all --fix-control -a'.
2015-07-28	revert 5af8f40d8f2c	Nilay Vaish

2015-07-26	cpu: implements vector registers	Nilay Vaish
	This adds a vector register type. The type is defined as a std::array of a fixed number of uint64_ts. The isa_parser.py has been modified to parse vector register operands and generate the required code. Different cpus have vector register files now.
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
	Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
2013-10-15	cpu: clean up architectural register classification	Steve Reinhardt
	Move from a poorly documented scheme where the mapping of unified architectural register indices to register classes is hardcoded all over to one where there's an enum for the register classes and a function that encapsulates the mapping.
2010-08-23	X86: Create a directory for files that define register indexes.	Gabe Black
	This is to help tidy up arch/x86. These files should not be used external to the ISA. --HG-- rename : src/arch/x86/apicregs.hh => src/arch/x86/regs/apic.hh rename : src/arch/x86/floatregs.hh => src/arch/x86/regs/float.hh rename : src/arch/x86/intregs.hh => src/arch/x86/regs/int.hh rename : src/arch/x86/miscregs.hh => src/arch/x86/regs/misc.hh rename : src/arch/x86/segmentregs.hh => src/arch/x86/regs/segment.hh
2010-05-23	copyright: Change HP copyright on x86 code to be more friendly	Nathan Binkert

2009-07-17	X86: Set up a named constant for the "fold bit" for int register indices.	Gabe Black

2009-07-17	X86: Shift some register flattening work into the decoder.	Gabe Black

2009-01-06	X86: Move the function that prints memory args into the inst base class.	Gabe Black

2009-01-06	X86: Change indentation on microop disassembly.	Gabe Black

2007-12-01	X86: Reorganize segmentation and implement segment selector movs.	Gabe Black
	--HG-- extra : convert_revision : 553c3ffeda1f5312cf02493f602e7d4ba2fe66e8
2007-11-12	X86: Various fixes to indexing segmentation related registers	Gabe Black
	--HG-- extra : convert_revision : 3d45da3a3fb38327582cfdfb72cfc4ce1b1d31af
2007-10-31	String constant const-ness changes to placate g++ 4.2.	Steve Reinhardt
	Also some bug fixes in MIPS ISA uncovered by g++ warnings (Python string compares don't work in C++!). --HG-- extra : convert_revision : b347cc0108f23890e9b73b3ee96059f0cea96cf6
2007-10-02	X86: Fix x87 floating point stack register indexing.	Gabe Black
	--HG-- extra : convert_revision : b515ec20cbfc50b38aa7da6cf4d465acf9054c08
2007-09-04	X86: Add floating point micro registers.	Gabe Black
	--HG-- extra : convert_revision : 442a5f8b9216638e4e6898f89eacb8695719e20f
2007-07-30	X86: Make register names in disassembly reflect high bytes.	Gabe Black
	--HG-- extra : convert_revision : e2891581e5504de0a2c8e5932fd22425cafd4fc7
2007-07-17	Make disassembled x86 register indices reflect their size.	Gabe Black
	This doesn't handle high byte register accesses. It also highlights the fact that address size isn't actually being calculated, and that the size a microop uses needs to be overridable from the microassembly. --HG-- extra : convert_revision : d495ac4f5756dc55a5f71953ff6963b3c030e6cb
2007-07-14	Pull some hard coded base classes out of the isa description.	Gabe Black
	--HG-- rename : src/arch/x86/isa/base.isa => src/arch/x86/isa/outputblock.isa extra : convert_revision : 7954e7d5eea3b5966c9e273a08bcd169a39f380c